参数资料
| 型号： | NCP5208DR2 |
| 厂商： | ON Semiconductor |
| 文件页数： | 8/9页 |
| 文件大小： | 0K |
| 描述： | IC REG TERM DDR-I/II 1.7V 8SOIC |
| 标准包装： | 2,500 |
| 应用： | 控制器，DDR，DDR2 |
| 输入电压： | 1.7 V ~ 5.5 V |
| 输出数： | 2 |
| 输出电压： | 0.9 V，1.25V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOICN |
| 包装： | 带卷 (TR) |
| 其它名称： | NCP5208DR2OS |
NCP5208
APPLICATIONS INFORMATION
PD?MAX + R?MAX
Typical Application Circuit
The NCP5208 is a highly integrated termination
regulator. For most applications, an input and output
capacitor and a pullup resistor for the power OK output, are
the only external components needed. For typical
application circuit, refer to Figure 1.
AVIN and VDDQ Supply
AVIN provides power for the device to operate. This
voltage must be kept clean and free from transients. A small
capacitor, 1.0 m F is recommended at this input to provide
the required supply filtering and ripple rejection. VDDQ is
primarily used to generate the internal voltage reference, so
any noise or transient at this pin will be directly reflected
at the VTT output. In order to avoid undesired interference
injected into this pin, appropriate de?coupling and careful
design of PCB layout is required.
Input Capacitor Selection
The NCP5208 does not require an input capacitor for
stability, however it is still recommended for better overall
performance during large load transients that can cause
sudden drop of the power rail voltage. The input capacitor
must be located as close as possible to the PVIN pin to
avoid a transient voltage dip affecting the quality of AVIN
and VDDQ. For typical DDR?I applications, a low ESR
electrolytic capacitor of 100 m F or larger is recommended.
By adding a small ceramic capacitor of 0.1 m F in parallel,
Thermal Dissipation
The NCP5208 is a linear regulator, any current flow
from/to VTT will result in internal power dissipation and
generating heat. In order to prevent un?wanted shutdown
of the device during operation, care should be taken to
de?rate the power capability according to the maximum
expected ambient temperature and power dissipation. The
maximum allowable internal temperature rise, T R?MAX
can be calculated from the equation in below:
TR?MAX + TJ?MAX * TA?MAX
Where T J?MAX is the maximum allowable junction
temperature and T A?MAX is the maximum expected
ambient temperature.
The maximum allowable power dissipation for a specific
condition is given by:
T
R q JA_T
Where P D?MAX is the maximum allowable power
dissipation and R q JA_T is Junction?to?Air thermal
resistance for specific package.
The thermal handling capability depends on several
variables. Increasing the thickness and area of the copper
and adding vias and airflow can improve the thermal
performance.
the best high frequency transient filtering will result. If the
device is located near the main supply bulk capacitors, the
input capacitance can be reduced accordingly.
Output Capacitor Selection
The NCP5208 is internally compensated and stable for any
output capacitor with capacitance greater than 220 m F and
with ESR ranging from 2 m W to 400 m W. The choice for this
output capacitor is determined solely by the application and
the requirements for load transient characteristic of VTT
output. As a general recommendation, the capacitance should
be larger than 220 m F with low ESR for SSTL and DDR
memory applications.
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相关代理商/技术参数 |
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| NCP5208DR2G | 功能描述:线性稳压器 - 标准 DDR-I/II Termination RoHS:否 制造商:STMicroelectronics 输出类型: 极性: 输出电压:1.8 V 输出电流:150 mA 负载调节: 最大输入电压:5.5 V 线路调整率: 最大工作温度:+ 125 C 安装风格:SMD/SMT 封装 / 箱体:SOT-323-5L |
| NCP5209/D | 制造商:未知厂家 制造商全称:未知厂家 功能描述:4-In-1 PWM Buck and Tri-Linear DDR Power Controller |
| NCP5210 | 制造商:ONSEMI 制造商全称:ON Semiconductor 功能描述:3-in-1 PWM Dual Buck and Linear DDR Power Controller |
| NCP5210/D | 制造商:未知厂家 制造商全称:未知厂家 功能描述:3-In-1 PWM Dual Buck and Linear DDR Power Controller |
| NCP5210MNR2 | 功能描述:DC/DC 开关控制器 3-in-1 DDR Power RoHS:否 制造商:Texas Instruments 输入电压:6 V to 100 V 开关频率: 输出电压:1.215 V to 80 V 输出电流:3.5 A 输出端数量:1 最大工作温度:+ 125 C 安装风格: 封装 / 箱体:CPAK |
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