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| 型号： | NCP5355DR2 |
| 厂商： | ON Semiconductor |
| 文件页数： | 8/10页 |
| 文件大小： | 0K |
| 描述： | IC DRVR MOSF SYNC BUCK 12V 8SOIC |
| 产品变化通告： | Product Obsolescence 11/Feb/2009 |
| 标准包装： | 1 |
| 配置： | 高端和低端，同步 |
| 输入类型： | 反相和非反相 |
| 延迟时间： | 30ns |
| 电流 - 峰： | 2A |
| 配置数： | 1 |
| 输出数： | 2 |
| 高端电压 - 最大（自引导启动）： | 26V |
| 电源电压： | 9.2 V ~ 13.2 V |
| 工作温度： | 0°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOICN |
| 包装： | 剪切带 (CT) |
| 其它名称： | NCP5355DR2OSCT |
NCP5355
Internal or External Bootstrap Diode
For convenience, a bootstrap diode is internally provided by
the NCP5355. This internal diode reduces system cost and
parts count.
However, this diode will have higher losses than a standard
small signal switching or Schottky diode. By using an external
Schottky diode (D BST in Figure 4) a small improvement in
efficiency can be achieved as illustrated by the graph in
Figure 5.
While the difference in efficiency is relatively small, this
difference represents heat loss in the driver and on average
driver temperature may be reduced by about 10 ° C if using an
external diode. If an external diode is used, it should be a
Schottky or switching diode. (For example:
ON Semiconductor Part Number BAT54HT1 or BAS16HT1.)
Adaptive Nonoverlap
The NCP5355 includes adaptive nonoverlap protection to
prevent top and bottom MOSFET cross conduction.
When CO goes low signaling TG to turn off the top
MOSFET, BG does not go high until the switch node
(DRN pin) has fallen below 5.0 V and a fixed amount of delay
(tpdh BG ) has elapsed. This ensures that the top MOSFET is off
before the bottom MOSFET is turned on.
When CO goes high signaling BG turn off the Bottom
MOSFET, TG does not go high until BG has fallen below a
threshold of 5.0 V and a fixed amount of time has elapsed
(tpdh TG ).
However, caution must be observed if too much gate
resistance and inductance is introduced into the path between
the IC and the gate of the low MOSFET. A condition can occur
where the NCP5355 will sense that BG has fallen below 5.0 V
while the gate end of the MOSFET still has not fallen low
enough to turn off the device. This parasitic gate impedance
between the driver and MOSFET can reduce the nonoverlap
time, and result in shoot?through currents.
Power Dissipation
Driver power dissipation may be approximated by the
following equation:
Ploss + fSW @ Vs @ (1.5 @ QTtopFETs ) QTbottomFETs)
) Vs @ Is
Safe design practice requires limiting the SO8 device power
dissipation to around 700 mW. Higher frequency designs may
require limiting the supply voltage (V s ) to less than 12 V to
maintain this limit.
Switch Node Overshoot and Ringing
Due to the high current sourcing capability of the
NCP5355, increased overshoot and ringing may be noticed
at the switch node (DRN pin). This can be reduced in several
ways.
One is by adding a low ESR 1.0 m F?10 m F ceramic
capacitor (C IN in Figure 4) from V IN to ground near each
Qtop. This capacitor should be located in such a manner as
to reduce the loop area of the switch node as shown in
Figure 6. A smaller loop area from C IN + to Qtop to Qbottom
and back to C IN ? will reduce the amount of ringing by
reducing the PCB inductance. If further reduction in
overshoot and ringing is desired, a Top MOSFET gate drive
resistor may be added (R GU in Figure 4) to slow the turn?on
of the Top MOSFET without increasing the turn?off time.
Layout Guidelines
When designing any switching regulator, the layout is
very important for proper operation. Gate drivers experience
high di/dt during switching, and the inductance of the gate
drive traces need to be minimized. Gate drive traces should
be kept as short and wide (25 to 30 mils) as practical, and
should have a return path directly below the gate trace. The
use of a ground plane is a desirable way to return ground
signals. Component location is very important. The boost
and the V s capacitor are the most critical, and need to be
placed as close as possible to the driver IC pins (C VS and
C BST in Figure 4) as shown in Figure 6. Higher frequency
designs will magnify any layout problems, and added
attention to these guidelines should be observed in designs
above 250 kHz.
Q TOP
where
f SW
V s
Q TtopFETs
is the switching frequency,
is the supply voltage,
is the sum of the Top MOSFETs total
C VS
R VS
gate charge,
Q TbottomFETs is the sum of the Bottom MOSFETs total
gate charge
U 1
D BST
I s
is the supply quiescent current, typically
around 5.0 mA
The 1.5 factor is a result of the internal bootstrap diode
whose loss is equivalent to the charge lost in turning on the Top
R GU
MOSFET. If an external diode is used to improve efficiency,
the 1.5 factor is replaced with 1.0 as this loss will now occur
Q BOTTOM
C BST
outside the package.
http://onsemi.com
8
Figure 6. Typical NCP5355 PCB Layout
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