参数资料
型号: NCP5381MNR2G
厂商: ON Semiconductor
文件页数: 11/35页
文件大小: 0K
描述: IC CTLR BUCK 2/3/4PHASE 40-QFN
产品变化通告: Specification Change MSL Updated 13/June/2008
Product Discontinuation 01/Oct/2008
标准包装: 2,500
应用: 控制器,Intel Pentium? IV
输入电压: 10.8 V ~ 13.2 V
输出数: 4
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 40-VFQFN 裸露焊盘
供应商设备封装: 40-QFN(7x7)
包装: 带卷 (TR)
NCP5381
ELECTRICAL CHARACTERISTICS
(0 ? C < T A < 70 ? C; 0 ? C < T J < 125 ? C; 10.8 V < V CC < 13.2 V; All DAC Codes; C VCC = 0.1 m F, F SW = 400 kHz, unless otherwise stated)
Parameter
Test Conditions
Min
Typ
Max
Units
Modulators (PWM Comparators)
Minimum Pulse Width
Magnitude of the PWM Ramp
0% Duty Cycle
100% Duty Cycle
Minimum PWM Linear Duty Cycle
(Note 1)
PWM Comparator Offset Mismatch
(Note 1)
Phase Angle Error
Propagation Delay (Note 1)
Propagation Delay (Note 1)
Fs = 400 kHz
COMP voltage when the PWM
outputs remain LO
COMP voltage when the PWM
outputs remain HI
F S = 400 kHz
Between any 2 phases,
F S = 400 kHz
Between adjacent phases,
F S = 400 kHz
Ramp/Comp crossing to Gx
high
Ramp/Comp crossing to Gx low
--
--
--
--
--
--
--15
--
--
30
1.0
1.3
2.3
90
--
--
20
20
40
--
--
--
--
40
15
--
--
ns
V
V
V
%
mV
?
ns
ns
PWM Outputs
Output High Voltage
Output Low Voltage
Rise Time
Fall Time
Output Impedance – LO State
G4 Gate Pin Source Current during
Phase Detect
Phase Detection Period
G4 Phase Detect Threshold Voltage
Sourcing 500 m A
Sinking 500 m A
C L = 20 pF, Δ Vo = 0.3 to 2.0 V
C L = 20 pF, Δ Vo = Vmax to
0.7 V
Resistance to GND (Gx = LO)
2.9
--
--
--
--
--
--
100
3.1
25
10
10
50
70
50
--
3.3
100
--
--
--
--
--
500
V
mV
ns
ns
Ω
m A
m s
mV
Gate Driver Enable (DRVON)
Output High Voltage
Output Low Voltage
Rise Time
Fall Time
Internal Pulldown Resistance
Sourcing 500 m A
Sinking 500 m A
C L (PCB) = 20 pF,
Δ Vo = 10% to 90%
C L (PCB) = 20 pF,
Δ Vo = 10% to 90%
V CC < UVLO Threshold
3.7
--
--
--
--
3.9
50
25
25
70
4.1
200
--
--
140
V
mV
ns
ns
k Ω
1. Guaranteed by design. Not tested in production.
http://onsemi.com
11
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