参数资料
型号: NCP5387MNR2G
厂商: ON Semiconductor
文件页数: 31/37页
文件大小: 0K
描述: IC CTLR BUCK 2/3/4PHASE 40-QFN
产品变化通告: Specification Change MSL Updated 28/Feb/2008
标准包装: 2,500
应用: 控制器,Intel VR10、VR11、AMD CPU
输入电压: 4.75 V ~ 5.25 V
输出数: 4
工作温度: 0°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 40-VFQFN 裸露焊盘
供应商设备封装: 40-QFN(6x6)
包装: 带卷 (TR)
NCP5387
Dynamic VID Testing
The VTT tool provides for VID stepping based on the
Intel Requirements. Select the Dynamic VID option.
Before enabling the test set the lowest VID to 0.5 V or
greater and set the highest VID to a value that is greater than
the lowest VID selection, then enable the test. See Figures
Design Methodology
Decoupling the V CC Pin on the IC
An RC input filter is required as shown in the V CC pin to
minimize supply noise on the IC. The resistor should be
sized such that it does not generate a large voltage drop
between the 5 V supply and the IC.
30 through 32.
Understanding Soft?Start
The controller supports two different startup routines. An
AMD ramp to the initial VID code, or a VR11 Ramp to the
1.1 V VID code, with a pause to capture the VID code then
resume ramping to target value based on an internal slew
rate limit. See Figures 33 and 34. The controller is designed
to regulate to the voltage on the SS pin until it reaches the
internal DAC voltage. The soft?start cap sets the initial
ramp rate using a typical 5.0 m A current. The typical value
to use for the soft?start cap (SS) is 0.01 m F. This results in
a ramp time to 1.1 V of 2.2 ms based on equation 1.
Css ^ iss
dtss
dvss
1.1 · V + dvss and i ss + 5 · m A
Figure 30. 1.6 to 0.5 Dynamic VID Response
2.2 · ms dtss
(eq. 1)
Css + 0.01 · m F
Figure 31. Dynamic VID Settling Time Rising
Figure 33. VR11 Startup
Figure 32. Dynamic VID Settling Time Falling
http://onsemi.com
31
Figure 34. AMD Startup
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