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参数资料
| 型号： | NCP5422EVB |
| 厂商： | ON Semiconductor |
| 文件页数： | 9/16页 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD FOR NCP5422 |
| 设计资源： | NCP5422EVB BOM NCP5422EVB Gerber Files NCP5422EVB Schematic |
| 标准包装： | 1 |
| 主要目的： | DC/DC，步降 |
| 输出及类型： | 2 个，非隔离式，（2 个电路） |
| 输出电压： | 1.5V，1.8V |
| 电流 - 输出： | 10A，10A |
| 输入电压： | 12V |
| 稳压器拓扑结构： | 降压 |
| 板类型： | 完全填充 |
| 已供物品： | 板 |
| 已用 IC / 零件： | NCP5422 |
| 其它名称： | NCP5422EVBOS |
NCP5422A
Selecting Feedback Divider Resistors
V OUT
R1
V FB
R2
Figure 7. Selecting Feedback Divider Resistors
Selection of Feedback Divider Resistors
Feedback divider resistors R1 and R2 are selected based
on a design trade-off between efficiency and output voltage
Figure 6. Hiccup Overcurrent Protection
Output Enable
On/Off control of the regulator outputs can be
implemented by pulling the COMP pins low. The COMP
accuracy. Both error amplifiers are referenced to 1.0 V, and
resistors R1 and R2 are connected from each channel's
output voltage to the inverting pin (V FB1(2) ) of each error
amplifier. To set the channel output voltage, first choose a
value for R1, and then R2 can be sized as follows:
Vout * 1
pins must be driven below the 0.425 V PWM comparator
offset voltage in order to disable the switching of the GATE
drivers.
R2 +
R1
1.0
The output voltage error due to the bias current of the error
Error + 1.6 · 10-6 · R1 · R2
VOUT ) VLFET ) VL
VIN ) VLFET * VHFET
DESIGN GUIDELINES
Definition of the design specifications
The output voltage tolerance can be affected by any or all
of the following reasons:
1.?buck regulator output voltage setpoint accuracy;
2.?output voltage change due to discharging or charging
of the bulk decoupling capacitors during a load
current transient;
3.?output voltage change due to the ESR and ESL of the
bulk and high frequency decoupling capacitors,
circuit traces, and vias;
4.?output voltage ripple and noise.
Budgeting the tolerance is left up to the designer who must
take into account all of the above effects and provide an
output voltage that will meet the specified tolerance at the
load.
The designer must also ensure that the regulator
component temperatures are kept within the manufacturer's
specified ratings at full load and maximum ambient
amplifier and the parallel combination of R1 and R2 can now
be estimated:
R1 ) R2
Reducing the size of R1 and R2 will reduce the output
voltage error, but increase the power dissipation.
Calculating Duty Cycle
The duty cycle of a buck converter (including parasitic
losses) is given by the formula:
Duty Cycle + D +
where:
V OUT = buck regulator output voltage;
V HFET = high side FET voltage drop due to R DS(ON) ;
V L = output inductor voltage drop due to inductor wire
DC resistance;
V IN = buck regulator input voltage;
V LFET = low side FET voltage drop due to R DS(ON) .
temperature.
http://onsemi.com
9
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