参数资料
| 型号： | NCS1002DR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 3/9页 |
| 文件大小： | 0K |
| 描述： | IC CTLR CV/CC SMPS 8-SOIC |
| 标准包装： | 2,500 |
| 输出隔离： | 隔离 |
| 输入电压： | 3 V ~ 32 V |
| 工作温度： | -40°C ~ 105°C |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOICN |
| 包装： | 带卷 (TR) |
| 其它名称： | NCS1002DR2G-ND NCS1002DR2GOSTR |
NCS1002
ELECTRICAL CHARACTERISTICS
Symbol
Characteristics
Conditions
Min
Typ
Max
Unit
I CC
I CC
Total Supply Current, excluding current in the Voltage Reference V CC = 5 V, no
load; ? 40 v T A v +105 ° C
Total Supply Current, excluding Current in the Voltage Reference V CC = 30 V, no
load; ? 40 v T A v +105 ° C
0.3
0.4
0.75
mA
mA
OP AMP 1 (OP AMP WITH NONINVERTING INPUT CONNECTED TO THE INTERNAL V ref )
(V CC = 5 V, T A = 25 ° C unless otherwise noted)
V IO
DV IO
l IB
AVD
Input Offset Voltage
Input Offset Voltage Drift ( ? 40 v T A v +105 ° C)
Input Bias Current (Inverting Input Only) T A = 25 ° C
Large Signal Voltage Gain (V CC = 15 V, R L = 2 k W ,
V ICM = 0 V)
T A = 25 ° C
? 40 v T A v +105 ° C
7.0
20
100
2.0
3.0
mV
mV
m V/ ° C
nA
V/mV
PSRR
I SOURCE
Power Supply Rejection (V CC = 5.0 V to 30 V, V OUT = 2 V)
Output Source Current (V CC = 15 V, V OUT = 2.0 V,
V id = 1 V)
80
20
100
40
dB
mA
I O
Short Circuit to GND (V CC = 15 V)
40
60
mA
I SINK
V OH
Output Current Sink (V id = ? 1 V)
Output Voltage Swing, High (V CC = 30 V)
V CC = +15 V, V OUT = 0.2 V
(Note 1)
V CC = +15 V, V OUT = 2 V
R L = 2 k W , T A = 25 ° C
1
10
26
10
20
27
mA
mA
V
? 40 v T A v +105 ° C
26
R L = 10 k W , T A = 25 ° C
? 40 v T A v +105 ° C
27
27
28
V OL
Output Voltage Swing, Low
R L = 10 k W , T A = 25 ° C
5.0
50
mV
? 40 v T A v +105 ° C
50
SR
GBP
THD
Slew Rate (AV = +1, V i = 0.5 V to 2 V, V CC = 15 V,
R L = 2 k W , C L = 100 pF)
Gain Bandwidth Product (V CC = 30 V, AV = +1, (Note 1)
R L = 2 k W , C L = 100 pF, f = 100 kHz, V IN = 10 mV PP )
Total Harmonic Distortion (f = 1 kHz, AV = 10,
R L = 2 k W , V CC = 30 V, V OUT = 2 V PP )
0.2
0.5
0.4
0.9
0.08
V/ m s
MHz
%
OP AMP 2 (INDEPENDENT OP AMP) (V CC = 5.0 V, T A = 25 ° C unless otherwise noted)
V IO
Input Offset Voltage
T A = 25 ° C
0.5
2.0
mV
? 40 v T A v +105 ° C
3.0
DV IO
Input Offset Voltage Drift ( ? 40 v T A v +105 ° C)
7.0
m V/ ° C
I IO
Input Offset Current
T A = 25 ° C
2.0
75
nA
? 40 v T A v +105 ° C
150
I B
Input Bias Current
T A = 25 ° C
20
150
nA
? 40 v T A v +105 ° C
200
AVD
PSRR
Large Signal Voltage Gain (V CC = 15 V,
R L = 2 k W , V OUT = 1.4 V to 11.4 V)
Power Supply Rejection (V CC = 5 V to 30 V)
T A = 25 ° C
? 40 v T A v +105 ° C
50
25
65
100
100
V/mV
dB
1. Guaranteed by design and/or characterization.
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