参数资料
| 型号： | NCS1002DR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 4/9页 |
| 文件大小： | 0K |
| 描述： | IC CTLR CV/CC SMPS 8-SOIC |
| 标准包装： | 2,500 |
| 输出隔离： | 隔离 |
| 输入电压： | 3 V ~ 32 V |
| 工作温度： | -40°C ~ 105°C |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOICN |
| 包装： | 带卷 (TR) |
| 其它名称： | NCS1002DR2G-ND NCS1002DR2GOSTR |
NCS1002
ELECTRICAL CHARACTERISTICS (continued)
Symbol
Characteristics
Conditions
Min
Typ
Max
Unit
OP AMP 2 (INDEPENDENT OP AMP) (continued) (V CC = 5.0 V, T A = 25 ° C unless otherwise noted)
V ICM
Input Common Mode Voltage Range (Note 2)
(V CC = +30 V)
T A = 25 ° C
0
V CC ?
1.5
V
? 40 v T A v +105 ° C
0
V CC ?
2.0
CMRR
Common Mode Rejection Ratio (Note 4)
0 to V CC ? 1.7 V,
T A = 25 ° C
70
85
dB
0 to V CC ? 2.2 V
? 40 v T A v +105 ° C
60
I SOURCE
Output Current Source (V CC = 15 V, V OUT = 2 V, V ID = +1 V)
20
40
mA
I O
Short ? Circuit to GND (V CC = 15 V)
40
60
mA
I SINK
V OH
Output Current Sink (V ID = ? 1 V)
Output Voltage Swing, High (V CC = 30 V)
V CC = +15 V, V OUT = 0.2 V
V CC = +15 V, V OUT = 2 V
R L = 2 k W , T A = 25 ° C
1
10
26
10
20
27
mA
mA
V
? 40 v T A v +105 ° C
26
R L = 10 k W , T A = 25 ° C
? 40 v T A v +105 ° C
27
27
28
V OL
Output Voltage Swing, Low
R L = 10 k W , T A = 25 ° C
5.0
50
mV
? 40 v T A v +105 ° C
50
SR
GBP
THD
e noise
Slew Rate (AV = +1, V i = 0.5 V to 3 V, V CC = 15 V, R L = 2 k W , C L = 100 pF)
Gain Bandwidth Product (V CC = 30 V, AV = +1,
R L = 2 k W , C L = 100 pF, f = 100 kHz, V IN = 10 mV PP ) (Note 4)
Total Harmonic Distortion (f = 1 kHz, AV = 10,
R L = 2 k W , V CC = 30 V, V OUT = 2 V PP )
Equivalent Input Noise Voltage (f = 1 kHz, R S = 100 W , V CC = 30 V)
0.2
0.5
0.4
0.9
0.08
50
V/ m s
MHz
%
nV/ √ Hz
VOLTAGE REFERENCE
I K
Cathode Current
0.075
100
mA
V ref
Reference Voltage (I K = 1 mA)
T A = 25 ° C
2.49
2.5
2.51
V
? 40 v T A v +105 ° C
2.48
2.5
2.52
D V ref
I min
I ZKA I
Reference Deviation over Temperature (V KA = V ref , I K = 10 mA, ? 40 v T A v
+105 ° C) (Note 4)
Minimum Cathode Current for Regulation (V KA w 2.45 V f )
Dynamic Impedance (Note 3)
(V KA = V ref , I K = 1 mA to 100 mA, f < 1 kHz)
7.0
40
0.2
30
75
0.5
mV
m A
W
2. The input common ? mode voltage of either input signal should not be allowed to go negative by more than 0.3 V. The upper end of the
common ? mode range is V CC ? 1.5 V. Both inputs can go to V CC + 0.3 V without damage.
3. The Dynamic Impedance is defined as l ZKA l = D V KA / D I K .
4. Guaranteed by design and/or characterization.
http://onsemi.com
4
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