参数资料
型号: NCV4276BDSADJR4G
厂商: ON Semiconductor
文件页数: 12/18页
文件大小: 0K
描述: IC REG LDO ADJ .4A D2PAK-5
标准包装: 800
稳压器拓扑结构: 正,可调式
输出电压: 2.5 V ~ 20 V
输入电压: 4.5 V ~ 40 V
电压 - 压降(标准): 0.25V @ 250mA
稳压器数量: 1
电流 - 输出: 400mA
电流 - 限制(最小): 400mA
工作温度: -40°C ~ 150°C
安装类型: 表面贴装
封装/外壳: TO-263-6,D²Pak(5 引线+接片),TO-263BA
供应商设备封装: D2PAK-5
包装: 带卷 (TR)
NCV4276B
back to the error amplifier by the voltage adjust pin VA.
The internal reference voltage is set to a temperature stable
reference of 2.5 V.
V I
I I
SMART
REGULATOR ?
I Q
V Q
PD(max) + [VI(max) * VQ(min)] IQ(max) )
R q JA + R q JC ) R q CS ) R q SA
R q JA + 150 C * A
T
PD
The output voltage is calculated from the following
formula. Ignoring the bias current into the VA pin:
VQ + [(R1 ) R2) * Vref] R2 (eq. 2)
Use R2 < 50 k to avoid significant voltage output errors
due to VA bias current.
Connecting VA directly to Q without R1 and R2 creates
an output voltage of 2.5 V.
Designers should consider the tolerance of R1 and R2
during the design phase.
The input voltage range for operation (pin 1) of the
adjustable version is between (V Q + 0.5 V) and 40 V.
Internal bias requirements dictate a minimum input voltage
of 4.5 V. The dropout voltage for output voltages less than
4.0 V is (4.5 V ? V Q ).
Calculating Power Dissipation
in a Single Output Linear Regulator
The maximum power dissipation for a single output
regulator (Figure 28) is:
(eq. 3)
) VI(max)Iq
where:
V I(max) is the maximum input voltage,
V Q(min) is the minimum output voltage,
I Q(max) is the maximum output current for the
application,
I q is the quiescent current the regulator
consumes at I Q(max) .
Once the value of P D(max) is known, the maximum
permissible value of R q JA can be calculated:
o
(eq. 4)
The value of R q JA can then be compared with those in the
package section of the data sheet. Those packages with
Control
Features
Iq
Figure 28. Single Output Regulator with Key
Performance Parameters Labeled
Heatsinks
A heatsink effectively increases the surface area of the
package to improve the flow of heat away from the IC and
into the surrounding air.
Each material in the heat flow path between the IC and
the outside environment will have a thermal resistance.
Like series electrical resistances, these resistances are
summed to determine the value of R q JA :
(eq. 5)
where:
R q JC is the junction-to-case thermal resistance,
R q CS is the case-to-heatsink thermal resistance,
R q SA is the heatsink-to-ambient thermal resistance.
R q JC appears in the package section of the data sheet.
Like R q JA , it too is a function of package type. R q CS and
R q SA are functions of the package type, heatsink and the
interface between them. These values appear in data sheets
of heatsink manufacturers.
Thermal, mounting, and heatsinking considerations are
discussed in the ON Semiconductor application note
AN1040/D.
Thermal Model
See pages 13 to 16 for detailed information about thermal
model parameters.
R q JA less than the calculated value in Equation 4 will keep
the die temperature below 150 ? C.
In some cases, none of the packages will be sufficient to
dissipate the heat generated by the IC, and an external
heatsink will be required.
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