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| 型号： | NCV431AIDR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 12/18页 |
| 文件大小： | 0K |
| 描述： | IC VREF SHUNT PREC ADJ 8-SOICN |
| 标准包装： | 1 |
| 基准类型： | 旁路，可调节，精度 |
| 输出电压： | 2.495 V ~ 36 V |
| 容差： | ±1% |
| 温度系数： | 标准值 50ppm/°C |
| 输入电压： | 2.495 V ~ 36 V |
| 通道数： | 1 |
| 电流 - 阴极： | 1mA |
| 电流 - 输出： | 100mA |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOICN |
| 包装： | 剪切带 (CT) |
| 其它名称： | NCV431AIDR2GOSCT |
TL431, A, B Series, NCV431A, B
V CC
R L
Input
C L
3
9.0 m F
15 k
Cathode
Ref
V ref
R P2
10 M
Go
1.0 m mho
8.25 k
1
500 k
1.78 V
+
-
R ref
16
G M
R GM
1.0 M
C P1
20 pF
R Z1
15.9 k
C P2
0.265 pF
Anode
2
Figure 31. Simplified TL431 Device Model
60
50
40
30
TL431 OPEN-LOOP VOLTAGE GAIN VERSUS FREQUENCY
Note that the transfer function now has an extra pole
formed by the load capacitance and load resistance.
Note that the crossover frequency in this case is about
250 kHz, having a phase margin of about ? 46 degrees.
Therefore, instability of this circuit is likely.
20
10
0
-10
-20
80
60
40
TL431 OPEN-LOOP BODE PLOT WITH LOAD CAP
10 1
10 2
10 3
10 4
10 5
10 6
10 7
f, FREQUENCY (Hz)
Figure 32. Example 1 Circuit Open Loop Gain Plot
20
Example 2.
I C = 7.5 mA, R L = 2.2 k W , C L = 0.01 m F. Cathode tied to
reference input pin. An examination of the data sheet
stability boundary curve (Figure 15) shows that this value of
0
-20
10 1
10 2
10 3
10 4
10 5
10 6
G + G R GoR +
load capacitance and cathode current is on the boundary.
Define the transfer gain.
The DC gain is:
M GM L
(2.323)(1.0 M)(1.25 m )(2200) + 6389 + 76 dB
The resulting open loop Bode plot is shown in Figure 33.
The asymptotic plot may be expressed as the following
equation:
f, FREQUENCY (Hz)
Figure 33. Example 2 Circuit Open Loop Gain Plot
With three poles, this system is unstable. The only hope
for stabilizing this circuit is to add a zero. However, that can
only be done by adding a series resistance to the output
capacitance, which will reduce its effectiveness as a noise
filter. Therefore, practically, in reference voltage
applications, the best solution appears to be to use a smaller
value of capacitance in low noise applications or a very
1 )
1 )
Av + 615
1 )
jf
8.0 kHz
jf
500 kHz
jf
60 kHz
1 )
jf
7.2 kHz
large value to provide noise filtering and a dominant pole
rolloff of the system.
http://onsemi.com
12
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