参数资料
| 型号： | NCV7340D13R2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 10/12页 |
| 文件大小： | 0K |
| 描述： | IC TXRX CAN HS LP 8SOIC |
| 标准包装： | 3,000 |
| 系列： | * |
NCV7340
http://onsemi.com
7
Table 6. CHARACTERISTICS VCC = 4.75 V to 5.25 V; TJ = 40 to +150°C; RLT = 60 W unless specified otherwise.
Symbol
Unit
Max
Typ
Min
Conditions
Parameter
BUS LINES (Pins CANH and CANL)
Io(sc) (CANL)
Short circuit output current at pin CANL for
the NCV7340D13(R2)G
VCANL = 36 V; VTxD = 0 V
45
70
100
mA
Short circuit output current at pin CANL for
NCV7340D12(R2)G & NCV7340D14(R2)G
VCANL = 36 V; VTxD = 0 V
45
70
120
mA
Vi(dif) (th)
Differential receiver threshold voltage (see
Figure 6)
5 V < VCANL < +12 V;
5 V < VCANH < +12 V;
0.5
0.7
0.9
V
Vihcm(dif) (th)
Differential receiver threshold voltage for
high commonmode (see Figure 6)
35 V < VCANL < +35 V;
35 V < VCANH < +35 V;
0.40
0.7
1.0
V
Vi(dif) (th)_STDBY
Differential receiver threshold voltage in
standby mode (see Figure 6)
12 V < VCANL < +12 V;
12 V < VCANH < +12 V;
0.4
0.8
1.15
V
Ri(cm) (CANH)
Commonmode input resistance at pin
CANH
15
26
37
k
W
Ri(cm) (CANL)
Commonmode input resistance at pin
CANL
15
26
37
k
W
Ri(cm) (m)
Matching between pin CANH and pin CANL
common mode input resistance
VCANH = VCANL
0.8
0
+0.8
%
Ri(dif)
Differential input resistance
25
50
75
k
W
Ci(CANH)
Input capacitance at pin CANH
VTxD = VCC; not tested
7.5
20
pF
Ci(CANL)
Input capacitance at pin CANL
VTxD = VCC; not tested
7.5
20
pF
Ci(dif)
Differential input capacitance
VTxD = VCC; not tested
3.75
10
pF
COMMONMODE STABILIZATION (Pin VSPLIT)
VSPLIT
Reference output voltage at pin VSPLIT
Normal mode;
500
mA < ISPLIT < 500 mA
0.3 x
VCC
0.7 x
VCC
ISPLIT(i)
VSPLIT leakage current
Standby mode
5
+5
mA
ISPLIT(lim)
VSPLIT limitation current
Normal mode
1.3
5.0
mA
THERMAL SHUTDOWN
TJ(sd)
Shutdown junction temperature
junction temperature rising
150
160
185
°C
td(TxDBUSon)
Delay TxD to bus active
Cl = 100 pF between
CANH to CANL
20
85
135
ns
td(TxDBUSoff)
Delay TxD to bus inactive
Cl = 100 pF between
CANH to CANL
5.0
60
105
ns
td(BUSonRXD)
Delay bus active to RxD
Crxd = 15 pF
25
55
105
ns
td(BUSoffRXD)
Delay bus inactive to RxD
Crxd = 15 pF
30
100
105
ns
tpd(recdom)
Propagation delay TxD to RxD from
recessive to dominant
Cl = 100 pF between
CANH to CANL
60
230
ns
td(domrec)
Propagation delay TxD to RxD from
dominant to recessive
Cl = 100 pF between
CANH to CANL
60
245
ns
td(stbnm)
Delay standby mode to normal mode
5.0
7.5
10
ms
tWake
Dominant time for wakeup via bus
Vdif(dom) > 1.4 V
0.75
2.5
5.0
ms
Vdif(dom) > 1.2 V
0.75
3
5.8
ms
tdwakerd
Delay to flag wake event (recessive to
dominant transitions) (See Figure 4)
Valid bus wake up event,
CRxD = 15 pF
1.0
3.4
10
ms
tdwakedr
Delay to flag end of wake event (dominant
to recessive transition) (See Figure 4)
Valid bus wake up event,
CRxD = 15 pF
0.5
2.9
6.0
ms
tWake(RxD)
Minimum pulse width on RxD (See Figure 4)
5
ms twake, CRxD = 15 pF
0.5
ms
tdom(TxD)
TxD dominant time for time out
VTxD = 0 V
300
650
1000
ms
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