参数资料
型号: NCV7341D21G
厂商: ON Semiconductor
文件页数: 7/18页
文件大小: 0K
描述: TXRX CAN HS LOW POWER 14SOIC
标准包装: 55
类型: 收发器
驱动器/接收器数: 1/1
规程: CAN
电源电压: 4.75 V ~ 5.25 V
安装类型: 表面贴装
封装/外壳: 14-SOIC(0.154",3.90mm 宽)
供应商设备封装: 14-SOIC
包装: 管件
NCV7341
http://onsemi.com
15
Table 9. AC CHARACTERISTICS
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
TIMING CHARACTERISTICS (Figure 6)
td(TxDBUSon)
Delay TxD to Bus Active
Setup According to Figure 8
40
85
105
ns
td(TxDBUSoff)
Delay TxD to Bus Inactive
Setup According to Figure 8
30
60
105
ns
td(BUSonRxD)
Delay Bus Active to RxD
Setup According to Figure 8
25
55
105
ns
td(BUSoffRxD)
Delay Bus Inactive to RxD
Setup According to Figure 8
40
65
105
ns
tpd(recdom)
Propagation Delay TxD to
RxD from Recessive to
Dominant
Setup According to Figure 8
90
130
230
ns
td(domrec)
Propagation Delay TxD to
RxD from Dominant to
Recessive
Setup According to Figure 8
90
140
245
ns
tUV(VCC)
Undervoltage Detection Time
on VCC
5.0
10
12.5
ms
tUV(VIO)
Undervoltage Detection Time
on VIO
5.0
10
12.5
ms
tdom(TxD)
TxD Dominant Timeout
300
600
1000
ms
th(min)
Minimum HoldTime for the
GotoSleep Mode
15
35
50
ms
tdom
Dominant Time for Wakeup
via the Bus
Vdif(CAN) > 1.4 V
0.75
2.5
5.0
ms
Vdif(CAN) > 1.2 V
0.75
3.0
5.8
ms
trec
Recessive Time for Wakeup
via the Bus
VBAT = 12 V
0.75
2.5
5.0
ms
tWAKE
Debounce Time for the
Wakeup via WAKE Pin
VBAT = 12 V
5.0
25
50
ms
terrdet
Minimum dominant bit time for
bus error detection
NCV7341D20 version
1
2
4
ms
MEASUREMENT DEFINITIONS AND SETUPS
CANH
CANL
TxD
RxD
dominant
0.9V
0.5V
recessive
0.7 x V
CC
V
i(dif) = VCANH VCANL
t
d(BUSonRxD)
PC20060915.2
0.3 X V
CC
t
pd(domrec)
50%
recessive
50%
t
d(BUSoffRxD)
t
d(TxDBUSoff)
t
d(TxDBUSon)
t
pd(recdom)
Figure 6. Timing Diagram for AC Characteristics
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