参数资料
型号: NCV8675DS50GEVB
厂商: ON Semiconductor
文件页数: 10/16页
文件大小: 0K
描述: EVAL BOARD FOR NCV8675DS50G
设计资源: NCV8675DS50GEVB Gerber Files
NCV8675 EVB Schematic
标准包装: 1
每 IC 通道数: 1 - 单
输出电压: 5V
电流 - 输出: 350mA
输入电压: 4.5 ~ 45 V
稳压器类型: 正,固定式
板类型: 完全填充
已供物品:
已用 IC / 零件: NCV8675
其它名称: NCV8675DS50GEVBOS
NCV8675
V in
C in
100 nF
C D
I D
V in
D
1
4
NCV8675
3
5
2
V out
RO
C out
22 m F
I RO
I out
V out
R EXT
5.0 K
V RO
47 nF
GND
I G
Figure 34. Application Circuits
Circuit Description
The NCV8675 is an integrated low dropout regulator that
provides 5.0 V 350 mA, or 3.3 V 350 mA protected output
and a signal for power on reset. The regulation is provided
by a PNP pass transistor controlled by an error amplifier
with a bandgap reference, which gives it the lowest possible
drop out voltage and best possible temperature stability. The
output current capability is 350 mA, and the base drive
quiescent current is controlled to prevent over saturation
when the input voltage is low or when the output is
overloaded. The regulator is protected by both current limit
and thermal shutdown. Thermal shutdown occurs above
150 ° C to protect the IC during overloads and extreme
ambient temperatures. The delay time for the reset output is
adjustable by selection of the timing capacitor. See
Figure 34, Test Circuit, for circuit element nomenclature
illustration.
Regulator
The error amplifier compares the reference voltage to a
sample of the output voltage (V out ) and drives the base of a
PNP series pass transistor by a buffer. The reference is a
bandgap design to give it a temperature ? stable output.
Saturation control of the PNP is a function of the load current
and input voltage. Oversaturation of the output power
device is prevented, and quiescent current in the ground pin
is minimized.
Regulator Stability Considerations
The input capacitor (C in ) is necessary to stabilize the input
impedance to avoid voltage line influences. The output
capacitor helps determine three main characteristics of a
linear regulator: startup delay, load transient response and
loop stability. The capacitor value and type should be based
on cost, availability, size and temperature constraints.
Ceramic, tantalum, or electrolytic capacitors of 22 m F, or
greater, are stable with very low ESR values. Refer to
Figure 2 for specific ESR ratings. The aluminum
electrolytic capacitor is the least expensive solution, but, if
the circuit operates at low temperatures ( ? 25 ° C to ? 40 ° C),
both the capacitance and ESR of the capacitor will vary
considerably. The capacitor manufacturer ’s data sheet
usually provides this information. The value for the output
capacitor C out shown in Figure 13, Test Circuit, should work
for most applications; however, it is not necessarily the
optimized solution.
Reset Output
The reset output is used as the power on indicator to the
microcontroller. This signal indicates when the output
voltage is suitable for reliable operation of the controller. It
pulls low when the output is not considered to be ready. RO
is pulled up to V out by an external resistor, typically 5.0 k W
in value. The input and output conditions that control the
Reset Output and the relative timing are illustrated in
Figure 35, Reset Timing. Output voltage regulation must be
maintained for the delay time before the reset output signals
a valid condition. The delay for the reset output is defined as
the amount of time it takes the timing capacitor on the delay
pin to charge from a residual voltage of 0 V to the upper
timing threshold voltage V DU of 1.3 V. The charging current
for this is I D of 4 m A and D pin voltage in steady state is
typically 2.4 V. By using typical IC parameters with a 47 nF
capacitor on the D Pin, the following time delay is derived:
t RD + C D * V DU I D
t RD + 47 nF * (1.3 V) 4 m A + 15.3 ms
Other time delays can be obtained by changing the C D
capacitor value. The Delay Time can be reduced by
decreasing the capacitance of C D . Using the formula above,
Delay can be reduced as desired. Leaving the Delay Pin
open is not desirable as it can result in unwanted signals
being coupled onto the pin.
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