参数资料
型号: NCV87721D5S50R4G
厂商: ON Semiconductor
文件页数: 13/17页
文件大小: 0K
描述: IC REG LDO 5V .35A D2PAK5
标准包装: 800
稳压器拓扑结构: 正,固定式
输出电压: 5V
输入电压: 5.5 V ~ 40 V
电压 - 压降(标准): 0.44V @ 350mA
稳压器数量: 1
电流 - 输出: 350mA
电流 - 限制(最小): 400mA
工作温度: -40°C ~ 150°C
安装类型: 表面贴装
封装/外壳: TO-263-6,D²Pak(5 引线+接片),TO-263BA
供应商设备封装: D2PAK-5
包装: 带卷 (TR)
NCV8772
APPLICATIONS INFORMATION
The NCV8772 regulator is self ? protected with internal
thermal shutdown and internal current limit. Typical
characteristics are shown in Figure 4 to Figure 33.
RESET DELAY AND RESET THRESHOLD OPTIONS
(DPAK ? 5 AND D2PAK ? 5)
Reset Delay Time Reset Threshold
Input Decoupling (C in )
A ceramic or tantalum 0.1 m F capacitor is recommended
and should be connected close to the NCV8772 package.
Higher capacitance and lower ESR will improve the overall
line and load transient response.
If extremely fast input voltage transients are expected then
appropriate input filter must be used in order to decrease
rising and/or falling edges below 50 V/ m s for proper
operation. The filter can be composed of several capacitors
in parallel.
Output Decoupling (C out )
The NCV8772 is a stable component and does not require
a minimum Equivalent Series Resistance (ESR) for the
output capacitor. Stability region of ESR vs Output Current
is shown in Figure 17. The minimum output decoupling
value is 1 m F and can be augmented to fulfill stringent load
transient requirements. The regulator works with ceramic
chip capacitors as well as tantalum devices. Larger values
improve noise rejection and load regulation transient
response.
NCV87721DT
NCV87721D5S
NCV87722DT
NCV87722D5S
NCV87723DT
NCV87723D5S
NCV87724DT
NCV87724D5S
NCV87725DT
NCV87725D5S
NCV8772ADT
NCV8772AD5S
NCV8772BDT
NCV8772BD5S
NCV8772CDT
NCV8772CD5S
NCV8772DDT
NCV8772DD5S
NCV8772EDT
NCV8772ED5S
8 ms
16 ms
32 ms
64 ms
128 ms
8 ms
16 ms
32 ms
64 ms
128 ms
93%
93%
93%
93%
93%
90%
90%
90%
90%
90%
Enable Operation
The Enable pin will turn the regulator on or off. The
threshold limits are covered in the electrical characteristics
NOTE:
The timing values can be selected from the following list:
8, 16, 32, 64, 128 ms. Contact factory for options not
included in ORDERING INFORMATION table on page 14.
table in this datasheet.
Reset Operation
A reset signal is provided on the Reset Output (RO) pin to
provide feedback to the microprocessor of an out of
regulation condition. The timing diagram of reset function
is shown in Figure 33. This is in the form of a logic signal on
RO. Output voltage conditions below the RESET threshold
cause RO to go low. The RO integrity is maintained down
to V out = 1.0 V. For 5 V voltage option, the Reset Output
(RO) circuitry includes internal pull ? up (30 k W ) connected
to the output (V out ) No external pull ? up is necessary.
Reset Delay Time Select (D2PAK ? 7 only)
Selection of the NCV8772yD7S devices and the state of
the DT pin determines the available Reset Delay times. The
part is designed for use with DT tied to ground or V out , but
may be controlled by any logic signal which provides a
threshold between 0.8 V and 2 V. The default condition for
an open DT pin is the slower Reset time (DT = GND
condition). Times are in pairs and are highlighted in the chart
below. Consult factory for availability. The Delay Time
select (DT) pin is logic level controlled and provides Reset
Delay time per the chart. Note the DT pin is sampled only
when RO is low, and changes to the DT pin when RO is high
will not effect the reset delay time.
http://onsemi.com
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