参数资料
| 型号： | NCV8843DG |
| 厂商： | ON Semiconductor |
| 文件页数： | 11/16页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK 1.5A 8SOIC |
| 标准包装： | 98 |
| 类型： | 降压（降压） |
| 输出数： | 1 |
| 输入电压： | 4.5 V ~ 40 V |
| PWM 型： | 混合物 |
| 频率 - 开关： | 340kHz |
| 电流 - 输出： | 1.5A |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 150°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 包装： | 管件 |
| 供应商设备封装： | 8-SOICN |
NCV8843
IP * P + O
) ) ESL( IN
) + ESL( IN )
VRIPPLE(ESL) + ESL(
Input capacitor type selection is determined by design
constraints and emphasis (such as cost, performance, or
size). Aluminum electrolytic capacitors are widely available
in a broad selection of values, and are generally economical.
Their ESR and ESL (effective series inductance), however,
are relatively high. Multiple capacitors are often connected
in parallel to reduce ESR, and ceramic capacitors added in
parallel to reduce high frequency noise. OS ? CON types
exhibit lower ESR. Solid tantalum capacitors combine low
ESR with small physical size.
Output Capacitor
In a buck converter, the requirements on the output
capacitor are not as critical as those on the input capacitor.
The current to the output capacitor comes from the inductor
and thus is triangular. In most applications, this makes the
RMS ripple current not an issue in selecting output
capacitors.
The output ripple voltage is the sum of a triangular wave
caused by ripple current flowing through ESR, and a square
Figure 15. Output Voltage Ripple Using Two 10 m F
Ceramic Capacitors in Parallel
Figure 17. Output Voltage Ripple Using One
100 m F OS ? CON
wave due to ESL. Capacitive reactance is assumed to be
small compared to ESR and ESL. The peak to peak ripple
current of the inductor is:
V (VIN * VO)
(VIN)(L)(fS)
V RIPPLE(ESR) , the output ripple due to the ESR, is equal
to the product of I P ? P and ESR. The voltage developed
across the ESL is proportional to the di/dt of the output
capacitor. It is realized that the di/dt of the output capacitor
is the same as the di/dt of the inductor current. Therefore,
when the switch turns on, the di/dt is equal to (V IN ? V O )/L,
and it becomes V O /L when the switch turns off. The total
ripple voltage induced by ESL can then be derived from
VO V * VO V
L L L
The total output ripple is the sum of the V RIPPLE(ESR) and
V RIPPLE(ESL) .
Figure 16. Output Voltage Ripple Using One 100 m F
POSCAP Capacitor
Figure 18. Output Voltage Ripple Using One
100 m F Tantalum Capacitor
http://onsemi.com
11
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