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参数资料
| 型号： | NE57814DD |
| 厂商： | NXP Semiconductors N.V. |
| 元件分类： | 基准电压源/电流源 |
| 英文描述： | DDR memory termination regulator with standby mode and enhanced efficiency |
| 封装： | NE57814DD<SOT786-2 (HSO8)|<<http://www.nxp.com/packages/SOT786-2.html<1<week 13, 2004,; |
| 文件页数： | 7/16页 |
| 文件大小： | 203K |
| 代理商： | NE57814DD |
Philips Semiconductors
Product data
NE57814
DDR memory termination regulator with
standby mode and enhanced efficiency
2003 Apr 03
7
TECHNICAL DISCUSSION
The NE57814 supplies power to the DDR memory bus termination
resistors at one-half the voltage supplied to the memory ICs or
DIMMs. The DDR memory bus can only have one output drive any
one bus line at any one time. So the load on the DDR termination
system is a matter of the number of bus lines being terminated and
the termination resistor values. The memory size (that is the MB) of
memory space is not relevant. A typical DDR memory system is
seen in Figure 8. Each bus input/output pin on the bus has a series
20
resistor connected to it. The bus is terminated to the DDR
terminator though a 27 to 50
resistance. The memory system will
then require current from the terminator output only when the
instantaneous value of the aggregate bus does not correspond to
equal amounts of 1s and 0s. When memory bus speeds are in the
200–300 MHz region, the period of any single bus state is extremely
small. This creates two bus loading conditions: the high frequency
condition which is caused by the instantaneous numbers of 1s and
0s, and the low frequency condition caused by mainly the address
bus being oriented towards the top or bottom of the memory space.
This creates two relatively independent output-filtering situations for
the DDR terminator: the high frequency bus speed, and the
low-frequency address skew of the processor system. Each should
be examined separately.
Figure 9 models the V
TT
loading condition of each bus line
equivalent circuit during operation and with terminating resistors.
This yields the worst case current loading equation:
I
O(max)
N
DDR
V
DD
2(R
T
R
S
)
Where:
N
DDR
is the total number of terminated control, address and data
lines within the DDR memory system (typically 192).
R
T
is the value of the terminating resistors.
R
S
is the value of the series resistors from the active output
driver.
Hence the worst-case current loading condition for the typical DDR
memory is 194 terminated bus lines, and there are either all 1s or all
0s for an instant. If the terminator resistances are R
T
= 27
and
R
S
= 20
, then this results in a momentary instantaneous output
current of either + or – 3.3 Amperes.
SL01879
V
TT
100 k
V
SS
ExtRefIn
OVERCURRENT
CONTROL
OVERTEMP
CONTROL
3
1
6
RefOut
8
4
V
D
5
V
DD
V
TT
SENSE
2
100 k
POWER
MANAGER
STANDBY
7
Figure 8. Functional diagram.
SL01880
V
D
V
D
V
DD
V
SS
V
SS
V
SS
V
TT
V
TT
R
T
R
S
R
T
R
S
A.
“1” DATA
B.
“0” DATA
Figure 9. The model for a single bus line for the DDR system.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| NE57814DD,518 | 功能描述:线性稳压器 - 标准 DDR TERMINATOR REG RoHS:否 制造商:STMicroelectronics 输出类型: 极性: 输出电压:1.8 V 输出电流:150 mA 负载调节: 最大输入电压:5.5 V 线路调整率: 最大工作温度:+ 125 C 安装风格:SMD/SMT 封装 / 箱体:SOT-323-5L |
| NE57814DD518 | 制造商:Rochester Electronics LLC 功能描述: 制造商:NXP 功能描述: 制造商:NXP Semiconductors 功能描述: |
| NE57835 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:TRANSISTOR | BJT | NPN | 11V V(BR)CEO | 30MA I(C) | SOT-173 |
| NE578D | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Compander |
| NE-58 | 制造商:Visual Communications Company (VCC) 功能描述:NE-58 /Refer New Part # F4A |
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