Semiconductor Components Industries, LLC, 2000
May, 2000 – Rev. 0
1
Publication Order Number:
NL74VCX16245/D
NL74VCX16245
Low-Voltage 1.8/2.5/3.3V
16-Bit Transceiver
With 3.6V–Tolerant Inputs and Outputs
(3–State, Non–Inverting)
The NL74VCX16245 is an advanced performance, non–inverting
16–bit transceiver. It is designed for very high–speed, very low–power
operation in 1.8V, 2.5V or 3.3V systems.
When operating at 2.5V (or 1.8V) the part is designed to tolerate
voltages it may encounter on either inputs or outputs when interfacing
to 3.3V busses. It is guaranteed to be over–voltage tolerant to 3.6V.
The VCX16245 is designed with byte control. It can be operated as
two separate octals, or with the controls tied together, as a 16–bit wide
function. The Transmit/Receive (T/Rn) inputs determine the direction
of data flow through the bi–directional transceiver. Transmit
(active–HIGH) enables data from A ports to B ports; Receive
(active–LOW) enables data from B to A ports. The Output Enable
inputs (OEn), when HIGH, disable both A and B ports by placing them
in a HIGH Z condition.
Designed for Low Voltage Operation: VCC = 1.65–3.6V
3.6V Tolerant Inputs and Outputs
High Speed Operation: 2.5ns max for 3.0 to 3.6V
3.0ns max for 2.3 to 2.7V
6.0ns max for 1.65 to 1.95V
Static Drive: ±24mA Drive at 3.0V
±18mA Drive at 2.3V
±6mA Drive at 1.65V
Supports Live Insertion and Withdrawal
IOFF Specification Guarantees High Impedance When VCC = 0V
Near Zero Static Supply Current in All Three Logic States (20A)
Substantially Reduces System Power Requirements
Latchup Performance Exceeds ±300mA @ 125°C
ESD Performance: Human Body Model >2000V; Machine Model
>200V
http://onsemi.com
MARKING DIAGRAM
A
= Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
TSSOP–48
DT SUFFIX
CASE 1201
1
48
NL74VCX16245DT
AWLYYWW
1
48
Device
Package
Shipping
ORDERING INFORMATION
NL74VCX16245DT
TSSOP
39 / Rail
NL74VCX16245DTR
TSSOP
2500 / Reel
PIN NAMES
Function
Output Enable Inputs
Transmit/Receive Inputs
Side A Inputs or 3–State Outputs
Side B Inputs or 3–State Outputs
Pins
OEn
T/Rn
A0–A15
B0–B15