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| 型号： | NOIL2SC1300A-GDC |
| 厂商： | ON Semiconductor |
| 文件页数： | 16/45页 |
| 文件大小： | 0K |
| 描述： | IC IMAGE SENSOR LUPA1300 168PGA |
| 标准包装： | 18 |
| 系列： | * |
| 象素大小： | 14µm x 5.2µm |
| 有源象素阵列： | 1280H x 1024V |
| 每秒帧数： | 30 |
| 电源电压： | 2.5V, 3.3V |
| 类型： | CMOS 成像 |
| 封装/外壳： | * |
| 供应商设备封装： | * |
| 包装： | * |
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NOIL2SM1300A
Data Block
The data block is positioned in between the analog front
end (output stage + ADCs) and the LVDS interface. It muxes
the outputs of 2 ADCs to one LVDS block and performs
some minor data handling:
? CRC calculation and insertion.
All data can be protected by a 10-bit checksum. The
CRC10 is calculated over all pixels between a Line
Start and a Line End. It is inserted in the data stream
after the line is completed, if input seq_data_crc is
enabled.The polynomial used is
(x^10+x^9+x^6+x^3+x^2+x+1) and 10 bits are
calculated in parallel. When a new line is started, the
seed is the first pixel value of a line. No CRC is
calculated for that value. From then on, every incoming
pixel is updated through the regular CRC.
? Training and test pattern generation
The most important registers in this block are:
Dataconfig. The dataconfig1[7:6] and dataconfig2[7:0]
registers insert a training pattern in the LVDS channels to
sync the LVDS receivers.
Datachannels. DatachannelX_1 and DatachannelX_2
(with X=0 to 12) are registers that allow you to enable or
disable the FPN correction (DatachannelX_1[1]), and
generate a test pattern if necessary (datachannelX_1[5:4]
and datachannelX_2[7:0]).
Sequencer Block
The sequencer block group registers allow enabling or
disabling image sensor features that are driven by the
onboard sequencer. This block consists of the following
registers:
Seqmode1. The seqmode1 registers have the following
subregisters:
Seqmode1[0]: Enables sequencer for image capture, must
be ‘1’ during image acquisition.
Seqmode1[1]: This subregister has two modes:
‘1’: In this default mode the integration timing is
generated on-chip.
‘0’: In this slave mode, the integration timing must be
generated through the int_time1, int_time2, and int_time3
pins.
Seqmode1[2]: This bit enables pipelined (0) or triggered
(1) mode.
Seqmode1[3]: Enable (1) or disable (0) subsampling.
Seqmode1[4]: This bit sets the type of subsampling
scheme used when subsampling is enabled.
‘1’: Color (1:1:0:0:1:1:0:0:1 … )
‘0’: Black and White (1:0:1:0:1)
Seqmode1[5]: This bit enables or disables the dual slope
integration.
Seqmode1[6]: This bit enables or disables the triple slope
integration.
Seqmode2. The seqmode2 register consists of only two
subregisters:
Seqmode2[4:0]: Default value after startup is ’10000’, but
this must be overwritten with the new value ’10001’
immediately after startup.
Seqmode3[6:5]: These two bits set the number of active
windows:
‘00’: 1 window
‘01’: 2 windows
‘10’: 3 windows
‘11’: 4 windows (max)
Seqmode3. The seqmode3 register consists of the
following subregisters:
Seqmode3[0]: This bit enables or disables the CRC10
generation on the data and sync channels
Seqmode3[1]: Not applicable
Seqmode3[2]: Enables or disables column FPN
correction
Seqmode3[5:3]: Enables or disables, and sets the number
of frames grabbed in nondestructive readout mode.
‘000’: Invalid
‘001’: Default, 1 reset, 1 sample
‘010’: 1reset, 2 samples
‘011’: 1 reset, 3 samples
Seqmode3[6]: Controls the granularity of the timer
settings (only for those that have ‘granularity selectable’ in
the description). As a result, all timer settings are set either
in number of applied clock cycles, or in the number of
‘readout lines’.
‘0’: expressed in number of lines
‘1’: expressed in clock cycles (multiplied by
2**seqmode4 [3:0])
Seqmode3[7]: Allows syncing of events that happen
outside of ROT to be delayed to the next ROT to avoid image
artifacts.
Seqmode4. This register consists of four subregisters:
Seqmode4[3:0]: Multiplier factor (2**seqmode4[3:0])
for the timers when working in clock cycle mode.
Seqmode4[5:4]: Selects the source signals to be put on the
digital test pins (monitor1, monitor2, and monitor3 pins)
“00”: integration time settings
“01”: EOS signals
“10”: frame sync signals
“11”: functional test mode
Seqmode4[6]: Enables (1) and disables (0) reverse X read
out.
Seqmode4[7]: Enables (1) and disables (0) reverse Y read
out.
Y1_start (60 and 61, 10 bit). These registers set the Y
start address for window 1 (default window).
X1_start (61, 6bit). This register sets the X start address
for window 1 (default window).
Y1_end (62 and 63, 10 bit). These registers set the Y end
address for window 1 (default window).
X1_kernels (63, 6 bit). This register sets the number of
kernels or X width to be read out for window 1 (default
window).
http://onsemi.com
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相关代理商/技术参数 |
参数描述 |
|---|---|
| NOIL2SM1300A-GDC | 功能描述:IC IMAGE SENSOR LUPA1300 168PGA RoHS:是 类别:传感器，转换器 >> 图像，相机 系列:* 标准包装:480 系列:- 象素大小:6.7µm x 6.7µm 有源象素阵列:768H x 488V 每秒帧数:52 电源电压:3.3V 类型:CMOS 成像 封装/外壳:48-QFP 供应商设备封装:48-QFP 包装:托盘 请注意:* 配用:4H2105-ND - HEADBOARD FOR KAC-004014H2104-ND - KIT EVAL FOR KAC-00401 其它名称:4H20954H2095-NDKAC-00401-CBC-LB-A0 |
| NOIL2SM1300A-GWC | 功能描述:IC IMAGE SENSOR LUPA1300 168PGA RoHS:是 类别:传感器，转换器 >> 图像，相机 系列:* 标准包装:480 系列:- 象素大小:6.7µm x 6.7µm 有源象素阵列:768H x 488V 每秒帧数:52 电源电压:3.3V 类型:CMOS 成像 封装/外壳:48-QFP 供应商设备封装:48-QFP 包装:托盘 请注意:* 配用:4H2105-ND - HEADBOARD FOR KAC-004014H2104-ND - KIT EVAL FOR KAC-00401 其它名称:4H20954H2095-NDKAC-00401-CBC-LB-A0 |
| NOIS1SC1000A-HHC | 制造商:ON Semiconductor 功能描述:STAR1000 COLOR JLCC84 - Trays 制造商:ON Semiconductor 功能描述:IC IMAGE SENSOR STAR1000 84JLCC |
| NOIS1SM0250A-HHC | 制造商:ON Semiconductor 功能描述:STAR250 JLCC84 - Trays 制造商:ON Semiconductor 功能描述:IC IMAGE SENSOR STAR250 84JLCC |
| NOIS1SM0250A-WWC | 制造商:ON Semiconductor 功能描述:STAR250 WAFER SALES - Waffle Pack |
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