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参数资料
| 型号： | NT5SV32M8AT |
| 厂商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 256Mb Synchronous DRAM |
| 中文描述： | 256Mb的同步DRAM |
| 文件页数： | 36/65页 |
| 文件大小： | 814K |
| 代理商： | NT5SV32M8AT |
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NT5SV64M4AT(L)
NT5SV32M8AT(L)
NT5SV16M16AT(L)
256Mb Synchronous DRAM
REV 1.0
May, 2001
36
NANYA TECHNOLOGY CORP
. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Operating, Standby, and Refresh Currents
(T
A
= 0 to +70
°
C, V
DD
= 3.3V
±
0.3V)
Parameter
Symbol
Test Condition
Speed
Units
Notes
-7K
-75B
-8B
Operating Current
I
CC1
1 bank operation
t
RC
= t
RC
(min), t
CK
= min
Active-Precharge command cycling with-
out burst operation
130
120
115
mA
1, 2, 3
Precharge Standby Current
in Power Down Mode
I
CC2P
CKE
≤
V
IL
(max), t
CK
= min,
CS = V
IH
(min)
2
2
2
mA
1
I
CC2PS
CKE
≤
V
IL
(max), t
CK
= Infinity,
CS = V
IH
(min)
2
2
2
mA
1
Precharge Standby Current
in Non-Power Down Mode
I
CC2N
CKE
≥
V
IH
(min), t
CK
= min,
CS = V
IH
(min)
30
30
20
mA
1, 5
I
CC2NS
CKE
≥
V
IH
(min), t
CK
= Infinity,
8
8
8
mA
1, 7
No Operating Current
(Active state: 4 bank)
I
CC3N
CKE
≥
V
IH
(min), t
CK
= min,
CS = V
IH
(min)
60
60
45
mA
1, 5
I
CC3P
CKE
≤
V
IL
(max), t
CK
= min,
6
6
6
mA
1, 6
Operating Current (Burst
Mode)
I
CC4
t
CK
= min,
Read/ Write command cycling,
Multiple banks active, gapless data, BL =
4
120
120
90
mA
1, 3, 4
Auto (CBR) Refresh Current
I
CC5
t
CK
= min, t
RC
= t
RC
(min)
CBR command cycling
175
175
155
mA
1
Self Refresh Current
I
CC6
CKE
≤
0.2V
SP
3
3
3
mA
1,8
LP
1.2
1.2
1.2
mA
8
1. Currents given are valid for a single device. .
2. These parameters depend on the cycle rate and are measured with the cycle determined by the minimum value of t
CK
and t
RC
. Input sig-
nals are changed up to three times during t
RC
(min).
3. The specified values are obtained with the output open.
4. Input signals are changed once during t
CK
(min).
5. Input signals are changed once during three clock cycles.
6. Active Standby Current will be higher if Clock Suspend is entered during a burst read cycle (add 1mA per DQ).
7. Input signals are stable.
8. SP : Standard power ; LP : Lower power
相关PDF资料 |
PDF描述 |
|---|---|
| NT5SV32M8AT-75B | 256Mb Synchronous DRAM |
| NT5SV32M8AT-7K | 256Mb Synchronous DRAM |
| NT5SV32M8AT-8B | 256Mb Synchronous DRAM |
| NT5SV64M4AT | 256Mb Synchronous DRAM |
| NT5SV64M4AT-7K | 256Mb Synchronous DRAM |
相关代理商/技术参数 |
参数描述 |
|---|---|
| NT5SV32M8AT-75B | 制造商:未知厂家 制造商全称:未知厂家 功能描述:256Mb Synchronous DRAM |
| NT5SV32M8AT-7K | 制造商:Nanya Technology Corporation 功能描述:32M X 8 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
| NT5SV32M8AT-8B | 制造商:未知厂家 制造商全称:未知厂家 功能描述:256Mb Synchronous DRAM |
| NT5SV4M16DT | 制造商:未知厂家 制造商全称:未知厂家 功能描述:64Mb Synchronous DRAM |
| NT5SV4M16DT-6K | 制造商:未知厂家 制造商全称:未知厂家 功能描述:64Mb Synchronous DRAM |
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