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参数资料
| 型号： | NTDV20N06T4G |
| 厂商： | ON Semiconductor |
| 文件页数： | 5/7页 |
| 文件大小： | 0K |
| 描述： | MOSFET N-CH 60V 20A DPAK |
| 标准包装： | 2,500 |
| FET 型： | MOSFET N 通道，金属氧化物 |
| FET 特点： | 标准 |
| 漏极至源极电压(Vdss)： | 60V |
| 电流 - 连续漏极(Id) @ 25° C： | 20A |
| 开态Rds（最大）@ Id, Vgs @ 25° C： | 46 毫欧 @ 10A，10V |
| Id 时的 Vgs(th)（最大）： | 4V @ 250µA |
| 闸电荷(Qg) @ Vgs： | 30nC @ 10V |
| 输入电容 (Ciss) @ Vds： | 1015pF @ 25V |
| 功率 - 最大： | 1.36W |
| 安装类型： | 表面贴装 |
| 封装/外壳： | TO-252-3，DPak（2 引线+接片），SC-63 |
| 供应商设备封装： | DPAK-3 |
| 包装： | 带卷 (TR) |
NTD20N06, NTDV20N06
12
10
Q T
1000
V DS = 30 V
I D = 20 A
V GS = 10 V
8
6
Q 1
Q 2
V GS
100
t r
t f
4
10
t d(off)
t d(on)
2
0
0
4
8
12
16
I D = 20 A
T J = 25 ° C
20
24
1
1
10
100
Q G , TOTAL GATE CHARGE (nC)
Figure 8. Gate ? To ? Source and Drain ? To ? Source
Voltage versus Total Charge
R G , GATE RESISTANCE (OHMS)
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN ? TO ? SOURCE DIODE CHARACTERISTICS
20
16
12
8
4
V GS = 0 V
T J = 25 ° C
0
0.6
0.7
0.8 0.9
1
V SD , SOURCE ? TO ? DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain ? to ? source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (T C ) of 25 ° C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance ?
General Data and Its Use.”
Switching between the off ? state and the on ? state may
traverse any load line provided neither rated peak current
(I DM ) nor rated voltage (V DSS ) is exceeded and the
transition time (t r ,t f ) do not exceed 10 m s. In addition the total
power averaged over a complete switching cycle must not
exceed (T J(MAX) ? T C )/(R q JC ).
A Power MOSFET designated E ? FET can be safely used
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non ? linearly with an
increase of peak current in avalanche and peak junction
temperature.
Although many E ? FETs can withstand the stress of
drain ? to ? source avalanche at currents up to rated pulsed
current (I DM ), the energy rating is specified at rated
continuous current (I D ), in accordance with industry custom.
The energy rating must be derated for temperature as shown
in the accompanying graph (Figure 12). Maximum energy at
currents below rated continuous I D can safely be assumed to
equal the values indicated.
in switching circuits with unclamped inductive loads. For
http://onsemi.com
5
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