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参数资料
| 型号： | NTE1639 |
| 厂商： | NTE Electronics, Inc. |
| 元件分类： | 运算放大器 |
| 英文描述： | Quad General-Purpose Operational Amplifier 14-SOIC 0 to 70 |
| 中文描述： | 集成电路CMOS时钟发生器/驱动器的BBDs |
| 文件页数： | 3/4页 |
| 文件大小： | 32K |
| 代理商： | NTE1639 |
Pin Descriptions:
Pin No.
Symbol
Pin Name
Description
1
GND
Ground
Connected to GND of the circuit.
2
CP1
Clock Output 1
This pin outputs a clock signal that is the reverse
phase of CP2 with a Duty Cycle of 1/2 the frequency
of oscillation.
3
V
DD
CP2
V
DD
apply
Clock Output 2
–
15V is applied
4
This pin outputs a clock signal that is a the reverse
phase of CP1
5
OX3
OSC connections to
C
1
, R
2
, and R
1
separately
R, C are connected for the In case of separate excita-
internal clock.
6
OX2
tion, OX3 and OX2 are
opened and OX1 is set to
OSC input.
7
OX1
8
V
GG OUT
V
GG
Voltage Output
–
14V is output. (V
DD
=
–
15V) V
GG OUT
= 14/15V
DD
.
The Maximum Clock Frequency:
The upper limit value of the clock frequency is determined by the load capacitance and power con-
sumption. The maximum power dissipation for the NTE1639 is P
D
= 200mW. If the clock frequency
of the load capacitance is increased, the power consumption will be increased. Accordingly, in order
to utilize this device with a dissipation less than the permissible value, it is necessary to select ade-
quate values for the clock frequency and load capacitance. By connecting a resistance to the clock
output pin, it is possible to increase the value of the maximum clock frequency without increasing dis-
sipation. Because the dissipation on the LSI side is lessened, part of the power consumption required
for driving the load capacitance is consumed by the series resistance.
Pin Connection Diagram
V
GG
(Out)
V
DD
1
2
3
4
GND
CP 1
CP 2
8
7
6
5
OX 1
OX 2
OX 3
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