参数资料
型号: OM11079
厂商: NXP Semiconductors
文件页数: 24/57页
文件大小: 0K
描述: MODULE DIMM LPC3250 ARM9
标准包装: 1
附件类型: 模块卡
适用于相关产品: ARM-57TS-LPC3250
相关产品: 622-1033-ND - KIT LCD TOUCH 5.7" FOR LPC2478
568-4743-ND - KIT LCD TOUCH 5.7" FOR LPC3250
568-4741-ND - KIT LCD TOUCH 5.7" FOR LPC2478
622-1030-ND - KIT LCD TOUCH 5.7" FOR LPC3250
622-1028-ND - KIT LCD TOUCH 5.7" FOR LPC2478
其它名称: 568-4744
LPC3220_30_40_50
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 20 October 2011
30 of 79
NXP Semiconductors
LPC3220/30/40/50
16/32-bit ARM microcontrollers
extended wait
Power-saving modes dynamically control EMC_CKE[1:0] and EMC_CLK.
Dynamic memory self-refresh mode supported by software.
Controller supports 2 k, 4 k, and 8 k row address synchronous memory parts. That is,
typical 512 MB, 256 MB, 128 MB, and 16 MB parts, with 8, 16, or 32 data bits per
device.
Two reset domains enable dynamic memory contents to be preserved over a soft
reset.
This controller does not support synchronous static memory devices (burst mode
devices).
7.6 AHB master peripherals
The LPC3220/30/40/50 implements four AHB master peripherals, which include a
General Purpose Direct Memory Access (GPDMA) controller, a 10/100 Ethernet Media
Access Controller (MAC), a Universal Serial Bus (USB) controller, and an LCD controller.
Each of these four peripherals contain an integral DMA controller optimized to support the
performance demands of the peripheral.
7.6.1 General Purpose DMA (GPDMA) controller
The GPDMA controller allows peripheral-to memory, memory-to-peripheral,
peripheral-to-peripheral, and memory-to-memory transactions. Each DMA stream
provides unidirectional serial DMA transfers for a single source and destination. For
example, a bidirectional port requires one stream for transmit and one for receive. The
source and destination areas can each be either a memory region or a peripheral, and
can be accessed through the same AHB master, or one area by each master. The DMA
controller supports the following peripheral device transfers.
Secure Digital (SD) Memory interface
High-speed UARTs
I2S0 and I2S1 ports
SPI1 and SPI2 interfaces
SSP0 and SSP1 interfaces
Memory
The DMA controls eight DMA channels with hardware prioritization. The DMA controller
interfaces to the system via two AHB bus masters, each with a full 32-bit data bus width.
DMA operations may be set up for 8-bit, 16-bit, and 32-bit data widths, and can be either
big-endian or little-endian. Incrementing or non-incrementing addressing for source and
destination are supported, as well as programmable DMA burst size. Scatter or gather
DMA is supported through the use of linked lists. This means that the source and
destination areas do not have to occupy contiguous areas of memory.
7.6.2 Ethernet MAC
The Ethernet block contains a full featured 10 Mbit/s or 100 Mbit/s Ethernet MAC
designed to provide optimized performance through the use of DMA hardware
acceleration. Features include a generous suite of control registers, half or full duplex
operation, flow control, control frames, hardware acceleration for transmit retry, receive
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