- 您现在的位置：买卖IC网 > PDF目录189449 > OR3T1256BC600I-DB (LATTICE SEMICONDUCTOR CORP) FPGA, 784 CLBS, 186000 GATES, PBGA600 PDF资料下载
参数资料
| 型号： | OR3T1256BC600I-DB |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 784 CLBS, 186000 GATES, PBGA600 |
| 封装： | PLASTIC, EBGA-600 |
| 文件页数： | 107/210页 |
| 文件大小： | 3438K |
| 代理商： | OR3T1256BC600I-DB |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页当前第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页第130页第131页第132页第133页第134页第135页第136页第137页第138页第139页第140页第141页第142页第143页第144页第145页第146页第147页第148页第149页第150页第151页第152页第153页第154页第155页第156页第157页第158页第159页第160页第161页第162页第163页第164页第165页第166页第167页第168页第169页第170页第171页第172页第173页第174页第175页第176页第177页第178页第179页第180页第181页第182页第183页第184页第185页第186页第187页第188页第189页第190页第191页第192页第193页第194页第195页第196页第197页第198页第199页第200页第201页第202页第203页第204页第205页第206页第207页第208页第209页第210页
Lattice Semiconductor
195
Data Sheet
December 2002
ORCA Series 3C and 3T FPGAs
Package Thermal Characteristics
There are four thermal parameters that are in common
use: ΘJA, ψJC, ΘJC, and ΘJB. It should be noted that all
the parameters are affected, to varying degrees, by
package design (including paddle size) and choice of
materials, the amount of copper in the test board or
system board, and system airow.
Table 76 contains the currently available thermal speci-
cations for FPGA packages mounted on both JEDEC
and non-JEDEC test boards. The thermal values for the
newer package types correspond to those packages
mounted on a JEDEC four-layer board. The values for
the older packages, however, correspond to those
packages mounted on a non-JEDEC, single-layer,
sparse copper board (see Note 2). It should also be
noted that the values for the older packages are con-
sidered conservative.
Θ
ΘJA
This is the thermal resistance from junction to ambient
(a.k.a. theta-JA, R-theta, etc.).
where TJ is the junction temperature, TA is the ambient
air temperature, and Q is the chip power.
Experimentally, ΘJA is determined when a special ther-
mal test die is assembled into the package of interest,
and the part is mounted on the thermal test board. The
diodes on the test chip are separately calibrated in an
oven. The package/board is placed either in a JEDEC
natural convection box or in the wind tunnel, the latter
for forced convection measurements. A controlled
amount of power (Q) is dissipated in the test chip’s
heater resistor, the chip’s temperature (TJ) is deter-
mined by the forward drop on the diodes, and the ambi-
ent temperature (TA) is noted. Note that ΘJA is
expressed in units of °C/watt.
ψ
ψJC
This JEDEC designated parameter correlates the junc-
tion temperature to the case temperature. It is generally
used to infer the junction temperature while the device
is operating in the system. It is not considered a true
thermal resistance, and it is dened by:
where TC is the case temperature at top dead center,
TJ is the junction temperature, and Q is the chip power.
During the ΘJA measurements described above,
besides the other parameters measured, an additional
temperature reading, TC, is made with a thermocouple
attached at top-dead-center of the case.
ψJC is also
expressed in units of °C/watt.
Θ
ΘJC
This is the thermal resistance from junction to case. It
is most often used when attaching a heat sink to the
top of the package. It is dened by:
The parameters in this equation have been dened
above. However, the measurements are performed
with the case of the part pressed against a water-
cooled heat sink so as to draw most of the heat gener-
ated by the chip out the top of the package. It is this dif-
ference in the measurement process that differentiates
ΘJC from ψJC. ΘJC is a true thermal resistance and is
expressed in units of °C/watt.
ΘJB
This is the thermal resistance from junction to board
(a.k.a. ΘJL). It is dened by:
where TB is the temperature of the board adjacent to a
lead measured with a thermocouple. The other param-
eters on the right-hand side have been dened above.
This is considered a true thermal resistance, and the
measurement is made with a water-cooled heat sink
pressed against the board so as to draw most of the
heat out of the leads. Note that ΘJB is expressed in
units of °C/watt, and that this parameter and the way it
is measured is still in JEDEC committee.
ΘJA
TJ
TA
–
Q
--------------------
=
ψJC
TJ
TC
–
Q
--------------------
=
ΘJC
TJ
TC
–
Q
--------------------
=
ΘJB
TJ
TB
–
Q
--------------------
=
相关PDF资料 |
PDF描述 |
|---|---|
| OR3T1257BC600-DB | FPGA, 784 CLBS, 186000 GATES, PBGA600 |
| OR3T55 | 3C and 3T Field-Programmable Gate Arrays |
| OR4E041BA352-DB | FPGA, 1296 CLBS, 380000 GATES, PBGA352 |
| OR4E041BM416-DB | FPGA, 1296 CLBS, 380000 GATES, PBGA416 |
| OR4E041BM680-DB | FPGA, 1296 CLBS, 380000 GATES, PBGA680 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| OR3T125-6PS208 | 制造商:AGERE 制造商全称:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3T1256PS208-DB | 功能描述:FPGA - 现场可编程门阵列 6272 LUT 342 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| OR3T125-6PS208I | 制造商:AGERE 制造商全称:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3T1256PS208I-DB | 功能描述:FPGA - 现场可编程门阵列 6272 LUT 342 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| OR3T125-6PS240 | 制造商:AGERE 制造商全称:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
发布紧急采购，3分钟左右您将得到回复。