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| 型号： | OR4E6-FPGA-EV |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 1/6页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR ORCA OR4E6 FPGA |
| 标准包装： | 1 |
| 系列： | ORCA® 4 系列 |
| 类型： | FPGA |
| 适用于相关产品： | OR4E6 |
| 所含物品： | 板 |
| 其它名称： | OR4E6FPGAEV |
Product Brief
January 15, 2002
ORCA ? Series 4
Field-Programmable Gate Arrays
Introduction
■
Traditional I/O selections:
— LVTTL and LVCMOS (3.3 V, 2.5 V, and 1.8 V)
Built on the Series 4 recon ? gurable embedded sys-
tem-on-chip (SoC) architecture, Lattice introduces its
new family of generic ? eld-programmable gate arrays
(FPGA). The high-performance and highly versatile
architecture brings a new dimension to bringing net-
work system designs to market in less time than ever
before. This new device family offers many new fea-
tures and architectural enhancements not available
in any earlier FPGA generations. Bringing together
highly ? exible SRAM-based programmable logic,
powerful system features, a rich hierarchy of routing
and interconnect resources, and meeting multiple
interface standards, the Series 4 FPGA accommo-
dates the most complex and high-performance intel-
lectual property (IP) network designs.
I/Os.
— Per pin-selectable I/O clamping diodes provide
3.3 V PCI compliance.
— Individually programmable drive capability:
24 mA sink/12 mA source, 12 mA sink/6 mA
source, or 6 mA sink/3 mA source.
— Two slew rates supported (fast and slew-lim-
ited).
— Fast-capture input latch and input ? ip- ? op
(FF)/latch for reduced input setup time and zero
hold time.
— Fast open-drain drive capability.
— Capability to register 3-state enable signal.
— Off-chip clock drive capability.
— Two-input function generator in output path.
■
New programmable high-speed I/O:
Programmable Features
— Single-ended: GTL, GTL+, PECL, SSTL3/2
(class I and II), HSTL (Class I, III, and IV), ZBT,
and DDR.
■
High-performance platform design:
— Double-ended: LDVS, bused-LVDS, and
— 0.16 μm 7-level metal technology.
— Internal performance of >250 MHz.
— I/O performance of >420 MHz.
— Meets multiple I/O interface standards.
— 1.5 V operation (30% less power than 1.8 V
operation) translates to greater performance.
LVPECL. Programmable (on/off) internal parallel
termination (100 ? ) also supported for these
I/Os.
Table 1. ORCA Series 4—Available FPGA Logic
Device
OR4E2
OR4E4
OR4E6
Rows
26
36
46
Columns
24
36
44
PFUs
624
1296
2024
User I/O
400
576
720
LUTs
4,992
10,368
16,192
EBR
Blocks
8
12
16
EBR Bits
(K)
74
111
147
Usable*
Gates (K)
260—515
380—800
515—1095
* The usable gate counts range from a logic-only gate count to a gate count assuming 20% of the PFUs/SLICs being used as RAMs. The
logic-only gate count includes each PFU/SLIC (counted as 108 gates/PFU), including 12 gates per LUT/FF pair (eight per PFU) and
12 gates per SLIC/FF pair (one per PFU). Each of the four PIO groups are counted as 16 gates (three FFs, fast-capture latch, output
logic, CLK, and I/O buffers). PFUs used as RAM are counted at four gates per bit, with each PFU capable of implementing a 32 x 4 RAM
(or 512 gates) per PFU. Embedded block RAM (EBR) is counted as four gates per bit, plus each block has an additional 25 K gates.
7 K gates are used for each PLL and 50K gates for the embedded system bus and microprocessor interface logic. Both the EBR and
PLLs are conservatively utilized in the gate count calculations.
Note: Devices are not pinout compatible with ORCA Series 2/3.
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