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参数资料
| 型号： | OR4E6-FPGA-EV |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 3/6页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR ORCA OR4E6 FPGA |
| 标准包装： | 1 |
| 系列： | ORCA® 4 系列 |
| 类型： | FPGA |
| 适用于相关产品： | OR4E6 |
| 所含物品： | 板 |
| 其它名称： | OR4E6FPGAEV |
Product Brief
ORCA Series 4
January 15, 2002
Field-Programmable Gate Arrays
System Features
■
New double-data rate (DDR) and zero-bus turn-
around (ZBT) memory interfaces support the latest
■
PCI local bus compliant.
high-speed memory interfaces.
■
Improved PowerPC ? /PowerQUICC MPC 860 and
PowerPC II MPC8260 high-speed synchronous
microprocessor interface can be used for con ? gura-
■
New 2x/4x uplink and downlink I/O capabilities inter-
face high-speed external I/Os to reduced speed
internal logic.
tion, readback, device control, and device status, as
well as for a general-purpose interface to the FPGA
logic, RAMs, and embedded standard cell blocks.
Glueless interface to synchronous PowerPC proces-
sors with user-con ? gurable address space is pro-
vided.
■
Meets universal test and operations PHY interface
for ATM (UTOPIA) Levels 1, 2, and 3. Also meets
proposed speci ? cations for UTOPIA level 4, POS-
PHY Level 3 (2.5 Gbits/s), and POS-PHY 4
(10 Gbits/s) interface standards for packet-over-
SONET as de ? ned by the Saturn Group.
■
New embedded AMBA ? speci ? cation 2.0 AHB sys-
tem bus ( ARM ? processor) facilitates communica-
tion among the microprocessor interface,
con ? guration logic, embedded block RAM, FPGA
■
ORCA Foundry development system software s
upported by industry-standard CAE tools for design
entry, synthesis, simulation, and timing analysis.
logic, and embedded standard cell blocks.
■
New network PLLs meet ITU-T G.811 speci ? cations
and provide clock conditioning for DS-1/E-1 and
STS-3/STM-1 applications.
■
Variable size bused readback of con ? guration data
capability with the built-in microprocessor interface
and system bus.
■
Internal, 3-state, bidirectional buses with simple con-
trol provided by the SLIC.
■
New clock routing structures for global and local
clocking signi ? cantly increases speed and reduces
skew (<200 ps for OR4E4).
■
New local clock routing structures allow creation of
localized clock trees.
■
Two new edge clock routing structures allow up to six
high-speed clocks on each edge of the device for
improved setup/hold and clock-to-out performance.
Lattice Semiconductor
3
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