参数资料
型号: P80C528FFP
厂商: NXP SEMICONDUCTORS
元件分类: 微控制器/微处理器
英文描述: CMOS single-chip 8-bit microcontroller
中文描述: 8-BIT, 16 MHz, MICROCONTROLLER, PDIP40
文件页数: 14/26页
文件大小: 447K
代理商: P80C528FFP
Philips Semiconductors
Product specification
80C528/83C528
CMOS single-chip 8-bit microcontrollers
1995 Feb 02
14
AC ELECTRICAL CHARACTERISTICS
1, 2
16MHz CLOCK
VARIABLE CLOCK
SYMBOL
FIGURE
PARAMETER
MIN
MAX
MIN
MAX
UNIT
1/t
CLCL
t
LHLL
t
AVLL
t
LLAX
t
LLIV
t
LLPL
t
PLPH
t
PLIV
t
PXIX
t
PXIZ
t
AVIV
t
PLAZ
Data Memory
1
Oscillator frequency
1.2
16
MHz
1
ALE pulse width
85
2t
CLCL
–40
t
CLCL
–55
t
CLCL
–35
ns
1
Address valid to ALE low
8
ns
1
Address hold after ALE low
28
ns
1
ALE low to valid instruction in
150
4t
CLCL
–100
ns
1
ALE low to PSEN low
23
t
CLCL
–40
3t
CLCL
–45
ns
1
PSEN pulse width
143
ns
1
PSEN low to valid instruction in
83
3t
CLCL
–105
ns
1
Input instruction hold after PSEN
0
0
ns
1
Input instruction float after PSEN
38
t
CLCL
–25
5t
CLCL
–105
10
ns
1
Address to valid instruction in
208
ns
1
PSEN low to address float
10
ns
t
RLRH
t
WLWH
t
RLDV
t
RHDX
t
RHDZ
t
LLDV
t
AVDV
t
LLWL
t
AVWL
t
QVWX
t
WHQX
t
RLAZ
t
WHLH
External Clock
2, 3
RD pulse width
275
6t
CLCL
–100
6t
CLCL
–100
ns
2, 3
WR pulse width
275
ns
2, 3
RD low to valid data in
148
5t
CLCL
–165
ns
2, 3
Data hold after RD
0
0
ns
2, 3
Data float after RD
55
2t
CLCL
–70
8t
CLCL
–150
9t
CLCL
–165
3t
CLCL
+50
ns
2, 3
ALE low to valid data in
350
ns
2, 3
Address to valid data in
398
ns
2, 3
ALE low to RD or WR low
138
238
3t
CLCL
–50
4t
CLCL
–130
t
CLCL
–60
t
CLCL
–50
ns
2, 3
Address valid to WR low or RD low
120
ns
2, 3
Data valid to WR transition
3
ns
2, 3
Data hold after WR
13
ns
2, 3
RD low to address float
0
0
ns
2, 3
RD or WR high to ALE high
23
103
t
CLCL
–40
t
CLCL
+40
ns
t
CHCX
t
CLCX
t
CLCH
t
CHCL
Shift Register
6
High time
20
20
ns
6
Low time
20
20
ns
6
Rise time
20
20
ns
6
Fall time
20
20
ns
t
XLXL
t
QVXH
t
XHQX
t
XHDX
t
XHDV
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
4
Serial port clock cycle time
750
12t
CLCL
10t
CLCL
–133
2t
CLCL
–117
0
ns
4
Output data setup to clock rising edge
492
ns
4
Output data hold after clock rising edge
8
ns
4
Input data hold after clock rising edge
0
ns
4
Clock rising edge to input data valid
492
10t
CLCL
–133
ns
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