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参数资料
| 型号： | P83C570AAR |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | Microcontrollers for NTSC TVs with On-Screen Display OSD and Closed Caption CC |
| 中文描述： | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PDIP52 |
| 文件页数： | 6/80页 |
| 文件大小： | 266K |
| 代理商： | P83C570AAR |
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1999 Jun 11
6
Philips Semiconductors
Product specification
Microcontrollers for NTSC TVs with On-Screen
Display (OSD) and Closed Caption (CC)
P8xCx70 family
5.2
Pin description
Table 1
SDIP52 package
SYMBOL
PIN
I/O
DESCRIPTION
P0.0/PWM8
to P0.7/PWM1
P1.0/AFT0
P1.1/AFT1
P1.2/AFT2
P1.3/PWM0
1 to 8
I/O
Port 0 lines P0.0 to P0.7 (open-drain, bidirectional); alternative functions 7-bit
PWM outputs.
Port 1 line P1.0; alternative function as 4-bit AFT0 input.
Port 1 line P1.1; alternative function as 4-bit AFT1 input.
Port 1 line P1.2; alternative function as 4-bit AFT2 input.
Port 1 I/O line P1.3 (open-drain, bidirectional); alternative function as 7-bit PWM0
output.
Ground line for digital circuits.
Port 2 lines P2.7 to P2.0 (open-drain, bidirectional).
Ground line for analog circuits.
Composite video input.
Data Slicer decoupling capacitor input, connect to V
SSA
via a 100 nF capacitor.
CVBS signal black level reference, connect to V
SSA
via a 100 nF capacitor.
CVBS signal reference current input, connect to V
SSA
via a 27 k
resistor.
Program Store Enable (active LOW); bonded out for testing purpose only.
External Access (active LOW); bonded out for testing purpose only. This pin is also
used for the 12.75 V programming voltage supply in OTP programming modes.
Address Latch Enable; bonded out for testing purpose only. This pin is also used
for programming pulses input in OTP programming modes.
Port 1 line P1.4 (open-drain, bidirectional).
Data Slicer reference high capacitor input, connect to V
SSA
via a 100 nF capacitor.
CC/OSD Blue colour current output.
CC/OSD Green colour current output.
CC/OSD Red colour current output.
CC/OSD fast blanking output.
TV horizontal sync input (for OSD synchronization).
TV vertical sync input (for OSD synchronization).
+5 V analog power supply.
+5 V digital power supply for peripherals.
Ground line for digital circuits.
System oscillator crystal output.
System oscillator crystal input.
Reset input (active HIGH).
+5 V digital power supply for CPU core.
Port 3 line P3.0; alternative function as external interrupt 1 input.
Port 3 line P3.1; alternative function as Counter 0 input.
Port 3 line P3.2; alternative function as external interrupt 0 input.
Port 3 line P3.3; alternative function as Counter 1 input.
9
10
11
12
I/O
I/O
I/O
I/O
V
SSD
P2.7 to P2.0
V
SSA
CVBS
STN
BLK
IREF
PSEN
V
PP
/EA
13
14 to 21
22
23
24
25
26
27
28
I/O
I
I
I
I
O
I
ALE/PROG
29
I/O
P1.4
REFH
B
G
R
FB
HSYNC
VSYNC
V
DDA
V
DDP
V
SSD
XO
XI
RESET
V
DDC
P3.0/INT1
P3.1/T0
P3.2/INT0
P3.3/T1
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
I/O
I
O
O
O
O
I
I
I
O
I
I
I/O
I/O
I/O
I/O
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