参数资料
型号: P87C51RA2BA,512
厂商: NXP Semiconductors
文件页数: 37/67页
文件大小: 0K
描述: IC 80C51 MCU 512 RAM 44PLCC
产品培训模块: Migrating from 8/16-Bit MCUs to 32-Bit ARMs
标准包装: 26
系列: 87C
核心处理器: 8051
芯体尺寸: 8-位
速度: 33MHz
连通性: EBI/EMI,UART/USART
外围设备: POR,PWM,WDT
输入/输出数: 32
程序存储器容量: 16KB(16K x 8)
程序存储器类型: OTP
RAM 容量: 512 x 8
电压 - 电源 (Vcc/Vdd): 2.7 V ~ 5.5 V
振荡器型: 内部
工作温度: 0°C ~ 70°C
封装/外壳: 44-LCC(J 形引线)
包装: 管件
其它名称: 568-7904-5
568-7904-5-ND
568-8355-5
935271889512
P87C51RA2BA
P87C51RA2BA,512-ND
P87C51RA2BA-ND
Philips Semiconductors
Product data
P87C51RA2/RB2/RC2/RD2
80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP
with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high
speed (30/33 MHz)
2003 Jan 24
42
ERAM
256 or 768 BYTES
UPPER
128 BYTES
INTERNAL RAM
LOWER
128 BYTES
INTERNAL RAM
SPECIAL
FUNCTION
REGISTER
100
FF
00
FF
00
80
EXTERNAL
DATA
MEMORY
FFFF
0000
SU01293
Figure 33. Internal and External Data Memory Address Space with EXTRAM = 0
HARDWARE WATCHDOG TIMER (ONE-TIME
ENABLED WITH RESET-OUT FOR
P87C51RA2/RB2/RC2/RD2)
The WDT is intended as a recovery method in situations where the
CPU may be subjected to software upset. The WDT consists of a
14-bit counter and the WatchDog Timer reset (WDTRST) SFR. The
WDT is disabled at reset. To enable the WDT, the user must write
01EH and 0E1H in sequence to the WDTRST, SFR location 0A6H.
When the WDT is enabled, it will increment every machine cycle
while the oscillator is running and there is no way to disable the
WDT except through reset (either hardware reset or WDT overflow
reset). When the WDT overflows, it will drive an output reset HIGH
pulse at the RST-pin (see the note below).
Using the WDT
To enable the WDT, the user must write 01EH and 0E1H in sequence
to the WDTRST, SFR location 0A6H. When the WDT is enabled, the
user needs to service it by writing 01EH and 0E1H to WDTRST to
avoid a WDT overflow. The 14-bit counter overflows when it reaches
16383 (3FFFH) and this will reset the device. When the WDT is
enabled, it will increment every machine cycle while the oscillator is
running. This means the user must reset the WDT at least every
16383 machine cycles. To reset the WDT, the user must write 01EH
and 0E1H to WDTRST. WDTRST is a write only register. The WDT
counter cannot be read or written. When the WDT overflows, it will
generate an output RESET pulse at the reset pin (see note below).
The RESET pulse duration is 98
× TOSC (6-clock mode; 196 in
12-clock mode), where TOSC = 1/fOSC. To make the best use of the
WDT, it should be serviced in those sections of code that will
periodically be executed within the time required to prevent a WDT
reset.
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