参数资料
型号: P87C51RA2BA,512
厂商: NXP Semiconductors
文件页数: 42/67页
文件大小: 0K
描述: IC 80C51 MCU 512 RAM 44PLCC
产品培训模块: Migrating from 8/16-Bit MCUs to 32-Bit ARMs
标准包装: 26
系列: 87C
核心处理器: 8051
芯体尺寸: 8-位
速度: 33MHz
连通性: EBI/EMI,UART/USART
外围设备: POR,PWM,WDT
输入/输出数: 32
程序存储器容量: 16KB(16K x 8)
程序存储器类型: OTP
RAM 容量: 512 x 8
电压 - 电源 (Vcc/Vdd): 2.7 V ~ 5.5 V
振荡器型: 内部
工作温度: 0°C ~ 70°C
封装/外壳: 44-LCC(J 形引线)
包装: 管件
其它名称: 568-7904-5
568-7904-5-ND
568-8355-5
935271889512
P87C51RA2BA
P87C51RA2BA,512-ND
P87C51RA2BA-ND
Philips Semiconductors
Product data
P87C51RA2/RB2/RC2/RD2
80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP
with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high
speed (30/33 MHz)
2003 Jan 24
47
AC ELECTRICAL CHARACTERISTICS (12-CLOCK MODE, 2.7 V TO 5.5 V OPERATION)
Tamb = 0 °C to +70 °C or –40 °C to +85 °C ; VCC = 2.7 V to 5.5 V, VSS = 0 V1,2,3,4
Symbol
Figure
Parameter
Limits
16 MHz Clock
Unit
MIN
MAX
MIN
MAX
1/tCLCL
38
Oscillator frequency
0
16
MHz
tLHLL
34
ALE pulse width
2tCLCL–10
115
ns
tAVLL
34
Address valid to ALE low
tCLCL –15
47.5
ns
tLLAX
34
Address hold after ALE low
tCLCL –25
37.5
ns
tLLIV
34
ALE low to valid instruction in
4 tCLCL –55
195
ns
tLLPL
34
ALE low to PSEN low
tCLCL –15
47.5
ns
tPLPH
34
PSEN pulse width
3 tCLCL –15
172.5
ns
tPLIV
34
PSEN low to valid instruction in
3 tCLCL –55
132.5
ns
tPXIX
34
Input instruction hold after PSEN
0
ns
tPXIZ
34
Input instruction float after PSEN
tCLCL –10
52.5
ns
tAVIV
34
Address to valid instruction in
5 tCLCL –50
262.5
ns
tPLAZ
34
PSEN low to address float
10
ns
Data Memory
tRLRH
35
RD pulse width
6 tCLCL –25
350
ns
tWLWH
36
WR pulse width
6 tCLCL –25
350
ns
tRLDV
35
RD low to valid data in
5 tCLCL –50
262.5
ns
tRHDX
35
Data hold after RD
0
ns
tRHDZ
35
Data float after RD
2 tCLCL –20
105
ns
tLLDV
35
ALE low to valid data in
8 tCLCL –55
445
ns
tAVDV
35
Address to valid data in
9 tCLCL –50
512.5
ns
tLLWL
35, 36
ALE low to RD or WR low
3 tCLCL –20
3 tCLCL +20
167.5
207.5
ns
tAVWL
35, 36
Address valid to WR low or RD low
4 tCLCL –20
230
ns
tQVWX
36
Data valid to WR transition
tCLCL –30
32.5
ns
tWHQX
36
Data hold after WR
tCLCL –20
42.5
ns
tQVWH
36
Data valid to WR high
7 tCLCL –10
427.5
ns
tRLAZ
35
RD low to address float
0
ns
tWHLH
35, 36
RD or WR high to ALE high
tCLCL –15
tCLCL +15
47.5
77.5
ns
External Clock
tCHCX
38
High time
0.32 tCLCL
tCLCL – tCLCX
ns
tCLCX
38
Low time
0.32 tCLCL
tCLCL – tCHCX
ns
tCLCH
38
Rise time
5
ns
tCHCL
38
Fall time
5
ns
Shift register
tXLXL
37
Serial port clock cycle time
12 tCLCL
750
ns
tQVXH
37
Output data setup to clock rising edge
10 tCLCL –25
600
ns
tXHQX
37
Output data hold after clock rising edge
2 tCLCL –15
110
ns
tXHDX
37
Input data hold after clock rising edge
0
ns
tXHDV
37
Clock rising edge to input data valid5
10 tCLCL –133
492
ns
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all outputs = 80 pF
3. Interfacing the microcontroller to devices with float time up to 45 ns is permitted. This limited bus contention will not cause damage to port 0
drivers.
4. Parts are guaranteed by design to operate down to 0 Hz.
5. Below 16 MHz this parameter is 8 tCLCL – 133.
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