参数资料
型号: P87C52X2FN,112
厂商: NXP Semiconductors
文件页数: 38/62页
文件大小: 0K
描述: IC 80C51 MCU 256 RAM 40DIP
产品培训模块: Migrating from 8/16-Bit MCUs to 32-Bit ARMs
标准包装: 9
系列: 87C
核心处理器: 8051
芯体尺寸: 8-位
速度: 33MHz
连通性: EBI/EMI,UART/USART
外围设备: POR
输入/输出数: 32
程序存储器容量: 8KB(8K x 8)
程序存储器类型: OTP
RAM 容量: 256 x 8
电压 - 电源 (Vcc/Vdd): 2.7 V ~ 5.5 V
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 40-DIP(0.600",15.24mm)
包装: 管件
其它名称: 568-7912-5
568-7912-5-ND
568-8361-5
935269602112
P87C52X2FN
P87C52X2FN,112-ND
P87C52X2FN-ND
Philips Semiconductors
Product data
P80C3xX2; P80C5xX2;
P87C5xX2
80C51 8-bit microcontroller family
4K/8K/16K/32K ROM/OTP, low voltage (2.7 to 5.5 V),
low power, high speed (30/33 MHz)
2003 Jan 24
43
AC ELECTRICAL CHARACTERISTICS (6-CLOCK MODE, 2.7 V TO 5.5 V OPERATION)
Tamb = 0 °C to +70 °C or –40 °C to +85 °C ; VCC=2.7 V to 5.5 V, VSS = 0 V1,2,3,4,5
Symbol
Figure
Parameter
Limits
16 MHz Clock
Unit
MIN
MAX
MIN
MAX
1/tCLCL
31
Oscillator frequency
0
16
MHz
tLHLL
27
ALE pulse width
tCLCL–10
52.5
ns
tAVLL
27
Address valid to ALE low
0.5 tCLCL –15
16.25
ns
tLLAX
27
Address hold after ALE low
0.5 tCLCL –25
6.25
ns
tLLIV
27
ALE low to valid instruction in
2 tCLCL –55
70
ns
tLLPL
27
ALE low to PSEN low
0.5 tCLCL –15
16.25
ns
tPLPH
27
PSEN pulse width
1.5 tCLCL –15
78.75
ns
tPLIV
27
PSEN low to valid instruction in
1.5 tCLCL –55
38.75
ns
tPXIX
27
Input instruction hold after PSEN
0
0
ns
tPXIZ
27
Input instruction float after PSEN
0.5 tCLCL –10
21.25
ns
tAVIV
27
Address to valid instruction in
2.5 tCLCL –50
101.25
ns
tPLAZ
27
PSEN low to address float
10
10
ns
Data Memory
tRLRH
28
RD pulse width
3 tCLCL –25
162.5
ns
tWLWH
29
WR pulse width
3 tCLCL –25
162.5
ns
tRLDV
28
RD low to valid data in
2.5 tCLCL –50
106.25
ns
tRHDX
28
Data hold after RD
0
0
ns
tRHDZ
28
Data float after RD
tCLCL –20
42.5
ns
tLLDV
28
ALE low to valid data in
4 tCLCL –55
195
ns
tAVDV
28
Address to valid data in
4.5 tCLCL –50
231.25
ns
tLLWL
28, 29
ALE low to RD or WR low
1.5 tCLCL –20
1.5 tCLCL +20
73.75
113.75
ns
tAVWL
28, 29
Address valid to WR low or RD low
2 tCLCL –20
105
ns
tQVWX
29
Data valid to WR transition
0.5 tCLCL –30
1.25
ns
tWHQX
29
Data hold after WR
0.5 tCLCL –20
11.25
ns
tQVWH
29
Data valid to WR high
3.5 tCLCL –10
208.75
ns
tRLAZ
28
RD low to address float
0
0
ns
tWHLH
28, 29
RD or WR high to ALE high
0.5 tCLCL –15
0.5 tCLCL +15
16.25
46.25
ns
External Clock
tCHCX
31
High time
0.4 tCLCL
tCLCL – tCLCX
ns
tCLCX
31
Low time
0.4 tCLCL
tCLCL – tCHCX
ns
tCLCH
31
Rise time
5
ns
tCHCL
31
Fall time
5
ns
Shift register
tXLXL
30
Serial port clock cycle time
6 tCLCL
375
ns
tQVXH
30
Output data setup to clock rising edge
5 tCLCL –25
287.5
ns
tXHQX
30
Output data hold after clock rising edge
tCLCL –15
47.5
ns
tXHDX
30
Input data hold after clock rising edge
0
0
ns
tXHDV
30
Clock rising edge to input data valid
5 tCLCL –133
179.5
ns
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN=100 pF, load capacitance for all outputs = 80 pF
3. Interfacing the microcontroller to devices with float time up to 45ns is permitted. This limited bus contention will not cause damage to port 0
drivers.
4. Parts are guaranteed by design to operate down to 0 Hz.
5. Data shown in the table are the best mathematical models for the set of measured values obtained in tests. If a particular parameter
calculated at a customer specified frequency has a negative value, it should be considered equal to zero.
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