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参数资料
| 型号： | P87CL883T |
| 厂商： | NXP Semiconductors N.V. |
| 英文描述： | TELX microcontrollers for CT0 handset/basestation applications |
| 中文描述： | TELX微控制器CT0手机/基站应用 |
| 文件页数： | 10/32页 |
| 文件大小： | 145K |
| 代理商： | P87CL883T |
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10
Philips Semiconductors
Product specification
TELX microcontrollers for CT0
handset/basestation applications
P8xCL883; P8xCL884
Tables 2 and 3 show the configuration register settings for
the 4 port output types.
The electrical characteristics of each output type can be
found in Chapter 8. The default port configuration after
reset is given in Table 3.
Table 2
Port Configuration Registers PnCFGA and PnCFGB (n = 0 to 3) settings
Note
1.
Mode changes may cause glitches to occur during transitions. When modifying both registers, WRITE instructions
should be carried out consecutively.
Table 3
Special Function Registers for port configurations/data
Notes
1.
This means that P0, P1.0 to P1.5 and P3 are initialized in Mode 1 (quasi-bidirectional, driving a weak HIGH) and the
I
2
C-bus ports P1.6 and P1.7 are initialized in Mode 0 (open-drain, not driven).
Port pin P3.4 is only available on P8xCL883.
2.
MODE
(1)
PnCFGA
PnCFGB
PORT OUTPUT MODE
NORMAL PORTS
I
2
C-BUS PORTS (P1.6 AND P1.7)
Mode 0
Mode 1
Mode 2
Mode 3
0
1
0
1
0
0
1
1
open-drain
quasi-bidirectional
high-impedance
push-pull
open-drain
open-drain
high-impedance
open-drain
REGISTER NAME
Port P0 output data
(1)
Port P0 configuration A
Port P0 configuration B
Port P1 output data
(1)
Port P1 configuration A
Port P1 configuration B
Port P3 output data
(1)
Port P3 configuration A
Port P3 configuration B
REGISTER MNEMONIC
SFR ADDRESS (HEX)
STATE AFTER RESET
P0
P0CFGA
P0CFGB
P1
P1CFGA
P1CFGB
P3
P3CFGA
P3CFGB
80
8E
8F
90
9E
9F
B0
BE
BF
1111 1111
1111 1111
0000 0000
1111 1111
0011 1111
0000 0000
XXX
1
XX
11
(2)
XXX
1
XX
11
(2)
XXX
0
XX
00
(2)
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