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参数资料
| 型号： | P87CL883T |
| 厂商： | NXP Semiconductors N.V. |
| 英文描述： | TELX microcontrollers for CT0 handset/basestation applications |
| 中文描述： | TELX微控制器CT0手机/基站应用 |
| 文件页数： | 9/32页 |
| 文件大小： | 145K |
| 代理商： | P87CL883T |
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9
Philips Semiconductors
Product specification
TELX microcontrollers for CT0
handset/basestation applications
P8xCL883; P8xCL884
Note
1.
Where: X = undefined state or not implemented bit.
6.2
I/O facilities
6.2.1
P
ORTS
The P8xCL883/P8xCL884 have 19 and 18 I/O lines
respectively, treated as 19 and 18 individually addressable
bits or as three parallel 8-bit addressable ports.
The alternative functions are detailed below:
Port 0 Offers no alternative functions.
Port 1 Used for a number of special functions:
P1.0 to P1.7 provides the inputs for the external
interrupts INT2 to INT9
P1.2/T2COMP for external activation and
Compare/Auto-reload output function of Timer 2
P1.4/CLK for the clock output
P1.6/SCL and P1.7/SDA for the I
2
C-bus interface
are real open-drain outputs or high-impedance;
no other port configurations are available.
Port 2 Not available.
Port 3 Pins can be configured individually to provide:
P3.0/RXD/data and P3.1/TXD/clock/MOUT0
which are serial port receiver input and
transmitter output (UART)
P3.4/T0 as counter input; available only in
P8xCL883.
To enable a Port pin alternative function, the Port bit latch
in its SFR must contain a logic 1.
WDT
WDCON
WDTIM
A5
FF
1010 0101
0000 0000
OTP interface
OAH
OAL
ODATA
OISYS
OTEST
D5
D4
D6
DC
D7
X
00
X XXXX
XXXX XXXX
XXXX XXXX
000
X
0000
0000 0000
Reserved locations; do not write
reserved
E7, FD
REGISTER
ADDRESS
(HEX)
RESET VALUE
(1)
Each port consists of a latch (Special Function Registers
P0 to P3), an output driver and input buffer. All ports have
internal pull-ups. Figure 3b shows that the strong
transistor ‘p1’ is turned on for only one oscillator period
after a LOW-to-HIGH transition in the port latch. When on,
it turns on ‘p3’ (a weak pull-up) through the inverter IN1.
This inverter and transistor ‘p3’ form a latch which holds
the logic 1.
Port P1.3 has LED drive capability.
6.2.2
P
ORT
I/O
CONFIGURATION
I/O port output configurations are determined by the
settings in port configuration SFRs. There are 2 SFRs for
each port: PnCFGA and PnCFGB, where ‘n’ indicates the
specific port number (0 to 3). One bit in each of the 2 SFRs
relates to the output setting for the corresponding port pin,
allowing any combination of the 2 output types to be mixed
on those port pins. For example, the output type of P1.3, is
controlled by the setting of bit 3 in the SFRs P1CFGA and
P1CFGB.
The port pins may be individually configured via SFRs with
one of the following modes (P1.6 and P1.7 can be
open-drain or high-impedance but never have any diodes
against V
DD
). These modes are also shown in Fig.3.
Mode 0 Open-drain; quasi-bidirectional I/O with
n-channel open-drain output. Use as an output
requires the connection of an external pull-up
resistor; e.g. Port 0 for external memory
accesses (EA = 0) or access above the built-in
memory boundary. The ESD protection diodes
against V
DD
and V
SS
are still present; see Fig.3b.
Except for the I
2
C-bus pins P1.6 and P1.7, ports
which are configured as open-drain still have a
protection diode to V
DD
.
Mode 1 Standard port; quasi-bidirectional I/O with
pull-up. The strong pull-up ‘p1’ is turned on for
only two oscillator periods after a LOW-to-HIGH
transition in the port latch. After these two
oscillator periods the port is only weakly driven
through ‘p2’ and ‘very weakly’ driven through ‘p3’
(see Fig.3b).
Mode 2 High-impedance; this mode turns off all output
drivers on a port. Thus, the pin will not source or
sink current and may be used as an input-only pin
with no internal drivers for an external device to
overcome (see Fig.3c).
Mode 3 Push-pull; output with drive capability in both
polarities. Under this mode, pins can only be
used as outputs (see Fig.3d).
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