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参数资料
| 型号： | P87LPC764FDH,512 |
| 厂商： | NXP Semiconductors |
| 文件页数： | 14/60页 |
| 文件大小： | 0K |
| 描述： | IC 80C51 MCU 4KB OTP 20TSSOP |
| 标准包装： | 75 |
| 系列： | LPC700 |
| 核心处理器： | 8051 |
| 芯体尺寸： | 8-位 |
| 速度： | 20MHz |
| 连通性： | I²C，UART/USART |
| 外围设备： | 欠压检测/复位，LED，POR，WDT |
| 输入/输出数： | 18 |
| 程序存储器容量： | 4KB（4K x 8） |
| 程序存储器类型： | OTP |
| RAM 容量： | 128 x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 2.7 V ~ 6 V |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 20-TSSOP（0.173"，4.40mm 宽） |
| 包装： | 管件 |
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Philips Semiconductors
Product data
P87LPC764
Low power, low price, low pin count (20 pin)
microcontroller with 4 kbyte OTP
2003 Sep 03
20
BIT
SYMBOL
FUNCTION
P2M1.7
P2S
When P2S = 1, this bit enables Schmitt trigger inputs on Port 2.
P2M1.6
P1S
When P1S = 1, this bit enables Schmitt trigger inputs on Port 1.
P2M1.5
P0S
When P0S = 1, this bit enables Schmitt trigger inputs on Port 0.
P2M1.4
ENCLK
When ENCLK is set and the 87LPC764 is configured to use the on-chip RC oscillator, a clock
output is enabled on the X2 pin (P2.0). Refer to the Oscillator section for details.
P2M1.3
T1OE
When set, the P0.7 pin is toggled whenever Timer 1 overflows. The output frequency is therefore
one half of the Timer 1 overflow rate. Refer to the Timer/Counters section for details.
P2M1.2
T0OE
When set, the P1.2 pin is toggled whenever Timer 0 overflows. The output frequency is therefore
one half of the Timer 0 overflow rate. Refer to the Timer/Counterssection for details.
P2M1.1, P2M1.0
—
These bits, along with the matching bits in the P2M2 register, control the output configuration of
P2.1 and P2.0 respectively, as shown in Table 4.
(P2M1.0)
SU01597
(P2M1.1)
T0OE
T1OE
ENCLK
P0S
P1S
P2S
0
1
2
3
4
5
6
7
P2M1
Reset Value: 00h
Not Bit Addressable
Address: A4h
Figure 13. Port 2 Mode Register 1 (P2M1)
Keyboard Interrupt (KBI)
The Keyboard Interrupt function is intended primarily to allow a
single interrupt to be generated when any key is pressed on a
keyboard or keypad connected to specific pins of the P87LPC764,
as shown in Figure 14. This interrupt may be used to wake up the
CPU from Idle or Power Down modes. This feature is particularly
useful in handheld, battery powered systems that need to carefully
manage power consumption yet also need to be convenient to use.
The P87LPC764 allows any or all pins of port 0 to be enabled to
cause this interrupt. Port pins are enabled by the setting of bits in
the KBI register, as shown in Figure 15. The Keyboard Interrupt Flag
(KBF) in the AUXR1 register is set when any enabled pin is pulled
low while the KBI interrupt function is active. An interrupt will
generated if it has been enabled. Note that the KBF bit must be
cleared by software.
Due to human time scales and the mechanical delay associated with
keyswitch closures, the KBI feature will typically allow the interrupt
service routine to poll port 0 in order to determine which key was
pressed, even if the processor has to wake up from Power Down
mode. Refer to the section on Power Reduction Modes for details.
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