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参数资料
| 型号： | P87LPC768BD,512 |
| 厂商： | NXP Semiconductors |
| 文件页数： | 17/65页 |
| 文件大小： | 0K |
| 描述： | IC 80C51 MCU 4K OTP 20-SOIC |
| 产品培训模块： | Migrating from 8/16-Bit MCUs to 32-Bit ARMs |
| 标准包装： | 38 |
| 系列： | LPC700 |
| 核心处理器： | 8051 |
| 芯体尺寸： | 8-位 |
| 速度： | 20MHz |
| 连通性： | I²C，UART/USART |
| 外围设备： | 欠压检测/复位，LED，POR，PWM，WDT |
| 输入/输出数： | 18 |
| 程序存储器容量： | 4KB（4K x 8） |
| 程序存储器类型： | OTP |
| RAM 容量： | 128 x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 2.7 V ~ 6 V |
| 数据转换器： | A/D 4x8b |
| 振荡器型： | 内部 |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 20-SOIC（0.295"，7.50mm 宽） |
| 包装： | 管件 |
| 产品目录页面： | 706 (CN2011-ZH PDF) |
| 其它名称： | 568-3218-5 935267360512 P87LPC768BD |
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Philips Semiconductors
Preliminary data
P87LPC768
Low power, low price, low pin count (20 pin) microcontroller
with 4 kB OTP 8-bit A/D, Pulse Width Modulator
2002 Mar 12
22
ARL
“Arbitration Loss” is 1 when transmit Active was set, but
this device lost arbitration to another transmitter.
Transmit Active is cleared when ARL is 1. There are
four separate cases in which ARL is set.
1. If the program sent a 1 or repeated start, but another
device sent a 0, or a stop, so that SDA is 0 at the rising
edge of SCL. (If the other device sent a stop, the setting
of ARL will be followed shortly by STP being set.)
2. If the program sent a 1, but another device sent a
repeated start, and it drove SDA low before SCL
could be driven low. (This type of ARL is always
accompanied by STR = 1.)
3. In master mode, if the program sent a repeated start,
but another device sent a 1, and it drove SCL low
before this device could drive SDA low.
4. In master mode, if the program sent stop, but it could
not be sent because another device sent a 0.
STR
“STaRt” is set to a 1 when an I2C start condition is
detected at a non-idle slave or at a master. (STR is not
set when an idle slave becomes active due to a start
bit; the slave has nothing useful to do until the rising
edge of SCL sets DRDY.)
STP
“SToP” is set to 1 when an I2C stop condition is
detected at a non-idle slave or at a master. (STP is not
set for a stop condition at an idle slave.)
MASTER
“MASTER” is 1 if this device is currently a master on
the I2C. MASTER is set when MASTRQ is 1 and the
bus is not busy (i.e., if a start bit hasn’t been
received since reset or a “Timer I” time-out, or if a stop
has been received since the last start). MASTER is
cleared when ARL is set, or after the software writes
MASTRQ = 0 and then XSTP = 1.
Writing I2CON
Typically, for each bit in an I2C message, a service routine waits for
ATN = 1. Based on DRDY, ARL, STR, and STP, and on the current
bit position in the message, it may then write I2CON with one or
more of the following bits, or it may read or write the I2DAT register.
CXA
Writing a 1 to “Clear Xmit Active” clears the Transmit
Active state. (Reading the I2DAT register also does this.)
Regarding Transmit Active
Transmit Active is set by writing the I2DAT register, or by writing
I2CON with XSTR = 1 or XSTP = 1. The I2C interface will only drive
the SDA line low when Transmit Active is set, and the ARL bit will
only be set to 1 when Transmit Active is set. Transmit Active is
cleared by reading the I2DAT register, or by writing I2CON with CXA
= 1. Transmit Active is automatically cleared when ARL is 1.
IDLE
Writing 1 to “IDLE” causes a slave’s I2C hardware to
ignore the I2C until the next start condition (but if
MASTRQ is 1, then a stop condition will cause this
device to become a master).
CDR
Writing a 1 to “Clear Data Ready” clears DRDY.
(Reading or writing the I2DAT register also does this.)
CARL
Writing a 1 to “Clear Arbitration Loss” clears the ARL bit.
CSTR
Writing a 1 to “Clear STaRt” clears the STR bit.
CSTP
Writing a 1 to “Clear SToP” clears the STP bit. Note that
if one or more of DRDY, ARL, STR, or STP is 1, the low
time of SCL is stretched until the service routine
responds by clearing them.
XSTR
Writing 1s to “Xmit repeated STaRt” and CDR tells the
I2C hardware to send a repeated start condition. This
should only be at a master. Note that XSTR need not
and should not be used to send an “initial”
(non-repeated) start; it is sent automatically by the I2C
hardware. Writing XSTR = 1 includes the effect of
writing I2DAT with XDAT = 1; it sets Transmit Active
and releases SDA to high during the SCL low time.
After SCL goes high, the I2C hardware waits for the
suitable minimum time and then drives SDA low to
make the start condition.
XSTP
Writing 1s to “Xmit SToP” and CDR tells the I2C
hardware to send a stop condition. This should only be
done at a master. If there are no more messages to
initiate, the service routine should clear the MASTRQ
bit in I2CFG to 0 before writing XSTP with 1. Writing
XSTP = 1 includes the effect of writing I2DAT with
XDAT = 0; it sets Transmit Active and drives SDA low
during the SCL low time. After SCL goes high, the I2C
hardware waits for the suitable minimum time and then
releases SDA to high to make the stop condition.
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相关代理商/技术参数 |
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|---|---|
| P87LPC768BN | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:Low power, low price, low pin count 20 pin microcontroller with 4 kB OTP 8-bit A/D,and Pulse Width Modulator |
| P87LPC768FD | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:Low power, low price, low pin count 20 pin microcontroller with 4 kB OTP 8-bit A/D,and Pulse Width Modulator |
| P87LPC768FD,512 | 功能描述:8位微控制器 -MCU 80C51 4K/128 OTP ADC RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
| P87LPC768FN | 制造商:NXP Semiconductors 功能描述:MCU 8-Bit 87LP 80C51 CISC 4KB EPROM 5V 20-Pin PDIP |
| P87LPC768FN,112 | 功能描述:8位微控制器 -MCU 80C51 4K/128 OTP ADC RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
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