参数资料
型号: P89C536NBAA
厂商: NXP SEMICONDUCTORS
元件分类: 微控制器/微处理器
英文描述: CMOS single-chip 8-bit microcontrollers with FLASH program memory
中文描述: 8-BIT, FLASH, 33 MHz, MICROCONTROLLER, PQCC44
封装: PLASTIC, MO-047, SOT-187-2, LCC-44
文件页数: 13/32页
文件大小: 269K
代理商: P89C536NBAA
Philips Semiconductors
Preliminary specification
89C536/89C538
80C51 8-bit microcontroller family
16K/64K/512 FLASH
1998 Apr 24
13
Interrupt Priority Structure
The 89C536/538 has a 6-source two-level interrupt structure (see
Table 7). There are 2 SFRs associated with the interrupts on the
89C536/538. They are the IE and IP. (See Figures 6 and 7.)
The function of the IPH SFR is simple and when combined with the
IP SFR determines the priority of each interrupt. The priority of each
interrupt is determined as shown in the following table:
PRIORITY BITS
IP.x
0
1
INTERRUPT PRIORITY LEVEL
Level 0 (lowest priority)
Level 1 (highest priority)
An interrupt will be serviced as long as an interrupt of equal or
higher priority is not already being serviced. If an interrupt of equal
or higher level priority is being serviced, the new interrupt will wait
until it is finished before being serviced. If a lower priority level
interrupt is being serviced, it will be stopped and the new interrupt
serviced. When the new interrupt is finished, the lower priority level
interrupt that was stopped will be completed.
Table 7.
Interrupt Table
SOURCE
X0
T0
X1
T1
SP
T2
POLLING PRIORITY
1
2
3
4
5
6
REQUEST BITS
IE0
TP0
IE1
TF1
R1, TI
TF2, EXF2
HARDWARE CLEAR
N (L)
1
Y
N (L)
Y
N
N
VECTOR ADDRESS
03H
0BH
13H
1BH
23H
2BH
Y (T)
2
Y (T)
NOTES:
1. L = Level activated
2. T = Transition activated
EX0
IE (0A8H)
Enable Bit = 1 enables the interrupt.
Enable Bit = 0 disables it.
BIT
IE.7
SYMBOL
EA
FUNCTION
Global disable bit. If EA = 0, all interrupts are disabled. If EA = 1, each interrupt can be individually
enabled or disabled by setting or clearing its enable bit.
Not implemented.
Timer 2 interrupt enable bit.
Serial Port interrupt enable bit.
Timer 1 interrupt enable bit.
External interrupt 1 enable bit.
Timer 0 interrupt enable bit.
External interrupt 0 enable bit.
IE.6
IE.5
IE.4
IE.3
IE.2
IE.1
IE.0
ET2
ES
ET1
EX1
ET0
EX0
SU00571
ET0
EX1
ET1
ES
ET2
EA
0
1
2
3
4
5
6
7
Figure 6.
IE Registers
PX0
IP (0B8H)
Priority Bit = 1 assigns higher priority
Priority Bit = 0 assigns lower priority
BIT
IP.7
IP.6
IP.5
IP.4
IP.3
IP.2
IP.1
IP.0
SYMBOL
PT2
PS
PT1
PX1
PT0
PX0
FUNCTION
Not implemented, reserved for future use.
Not implemented, reserved for future use.
Timer 2 interrupt priority bit.
Serial Port interrupt priority bit.
Timer 1 interrupt priority bit.
External interrupt 1 priority bit.
Timer 0 interrupt priority bit.
External interrupt 0 priority bit.
SU00572
PT0
PX1
PT1
PS
PT2
0
1
2
3
4
5
6
7
Figure 7.
IP Registers
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