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参数资料
| 型号： | P89LPC9251FDH |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-bit microcontroller with accelerated two-clock 80C51 core 2 kB-4 kB-8 kB 3 V byte-erasable flash with 8-bit ADC |
| 中文描述： | MICROCONTROLLER, PDSO20 |
| 封装： | 4.40 MM, PLASTIC, MO-153, SOT360-1, TSSOP-20 |
| 文件页数： | 22/75页 |
| 文件大小： | 1612K |
| 代理商： | P89LPC9251FDH |
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P89LPC92X1
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 1 December 2010
29 of 75
NXP Semiconductors
P89LPC9201/9211/922A1/9241/
8-bit microcontroller with 8-bit ADC
7.13 Memory organization
The various P89LPC9201/9211/922A1/9241/9251 memory spaces are as follows:
DATA
128 bytes of internal data memory space (00H:7FH) accessed via direct or indirect
addressing, using instructions other than MOVX and MOVC. All or part of the Stack
may be in this area.
IDATA
Indirect Data. 256 bytes of internal data memory space (00H:FFH) accessed via
indirect addressing using instructions other than MOVX and MOVC. All or part of the
Stack may be in this area. This area includes the DATA area and the 128 bytes
immediately above it.
SFR
Special Function Registers. Selected CPU registers and peripheral control and status
registers, accessible only via direct addressing.
CODE
64 kB of Code memory space, accessed as part of program execution and via the
MOVC instruction. The P89LPC9201/9211/922A1/9241/9251 has 2 kB/4 kB/8 kB of
on-chip Code memory.
7.14 Data RAM arrangement
The 256 bytes of on-chip RAM are organized as shown in Table 8.
7.15 Interrupts
The P89LPC9201/9211/922A1/9241/9251 uses a four priority level interrupt structure.
This allows great flexibility in controlling the handling of the many interrupt sources. The
P89LPC9201/9211/922A1/9241/9251 supports 12/13 interrupt sources: external
interrupts 0 and 1, timers 0 and 1, serial port TX, serial port RX, combined serial port
RX/TX, brownout detect, watchdog/RTC, I2C-bus, keyboard, comparators 1 and 2, A/D
Converter (P89LPC9241/9251).
Each interrupt source can be individually enabled or disabled by setting or clearing a bit in
the interrupt enable registers IEN0 or IEN1. The IEN0 register also contains a global
disable bit, EA, which disables all interrupts.
Each interrupt source can be individually programmed to one of four priority levels by
setting or clearing bits in the interrupt priority registers IP0, IP0H, IP1 and IP1H. An
interrupt service routine in progress can be interrupted by a higher priority interrupt, but
not by another interrupt of the same or lower priority. The highest priority interrupt service
cannot be interrupted by any other interrupt source. If two requests of different priority
levels are pending at the start of an instruction, the request of higher priority level is
serviced.
Table 8.
On-chip data memory usages
Type
Data RAM
Size (bytes)
DATA
Memory that can be addressed directly and indirectly
128
IDATA
Memory that can be addressed indirectly
256
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相关代理商/技术参数 |
参数描述 |
|---|---|
| P89LPC9251FDH,112 | 功能描述:8位微控制器 -MCU MCU 8-Bit CISC 8KB Flash2.5V/3.3V 20Pin RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
| P89LPC925FDH | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:8-bit microcontrollers with accelerated two-clock 80C51 core 4 kB/8 kB 3 V low-power Flash with 8-bit A/D converter |
| P89LPC925FDH,529 | 功能描述:8位微控制器 -MCU 80C51 8K FL 256B RAM RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
| P89LPC925FDH-S | 制造商:NXP Semiconductors 功能描述:MCU 8-bit P89 80C51 CISC 8KB Flash 2.5V/3.3V 20-Pin TSSOP |
| P89LPC925FN,129 | 功能描述:8位微控制器 -MCU 8K FL/256B RAM/I2C/UART/ADC RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
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