参数资料
型号: P89LPC9251FDH
厂商: NXP SEMICONDUCTORS
元件分类: 微控制器/微处理器
英文描述: 8-bit microcontroller with accelerated two-clock 80C51 core 2 kB-4 kB-8 kB 3 V byte-erasable flash with 8-bit ADC
中文描述: MICROCONTROLLER, PDSO20
封装: 4.40 MM, PLASTIC, MO-153, SOT360-1, TSSOP-20
文件页数: 59/75页
文件大小: 1612K
代理商: P89LPC9251FDH
P89LPC92X1
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 1 December 2010
62 of 75
NXP Semiconductors
P89LPC9201/9211/922A1/9241/
8-bit microcontroller with 8-bit ADC
11. Dynamic characteristics
[1]
Parameters are valid over operating temperature range unless otherwise specified.
[2]
Parts are tested to 2 MHz, but are guaranteed to operate down to 0 Hz.
Table 14.
Dynamic characteristics (12 MHz)
VDD = 2.4 V to 3.6 V unless otherwise specified.
Tamb = 40 °Cto+85 °C for industrial applications, unless otherwise specified.[1][2]
Symbol
Parameter
Conditions
Variable clock
fosc =12MHz
Unit
Min
Max
Min
Max
fosc(RC)
internal RC oscillator
frequency
nominal f = 7.3728 MHz
trimmed to
± 1% at
Tamb =25 °C; clock
doubler option = OFF
(default)
7.189
7.557
7.189
7.557
MHz
nominal f = 14.7456 MHz;
clock doubler option = ON,
VDD = 2.7 V to 3.6 V
14.378
15.114
14.378 15.114 MHz
fosc(WD)
internal watchdog
oscillator frequency
Tamb =25 °C
380
420
380
420
kHz
fosc
oscillator frequency
0
12
-
MHz
Tcy(clk)
clock cycle time
83
-
ns
fCLKLP
low-power select clock
frequency
08
-
MHz
Glitch filter
tgr
glitch rejection time
P1.5/RST pin
-
50
-
50
ns
any pin except P1.5/RST
-
15
-
15
ns
tsa
signal acceptance time
P1.5/RST pin
125
-
125
-
ns
any pin except P1.5/RST
50
-
50
-
ns
External clock
tCHCX
clock HIGH time
33
Tcy(clk) tCLCX
33
-
ns
tCLCX
clock LOW time
33
Tcy(clk) tCHCX
33
-
ns
tCLCH
clock rise time
-8
-
8
ns
tCHCL
clock fall time
-8
-
8
ns
Shift register (UART mode 0)
TXLXL
serial port clock cycle
time
16Tcy(clk)
-
1333
-
ns
tQVXH
output data set-up to
clock rising edge time
13Tcy(clk)
-
1083
-
ns
tXHQX
output data hold after
clock rising edge time
-Tcy(clk) + 20
-
103
ns
tXHDX
input data hold after
clock rising edge time
-0
-
0
ns
tXHDV
input data valid to clock
rising edge time
150
-
150
-
ns
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