参数资料
型号: P89LPC930FDH
厂商: NXP Semiconductors N.V.
元件分类: 8位微控制器
英文描述: 8-bit microcontrollers with two-clock 80C51 core 4 kB-8 kB 3 V Flash with 256-byte data RAM
封装: P89LPC930FDH<SOT361-1 (TSSOP28)|<<http://www.nxp.com/packages/SOT361-1.html<1<week 47, 2004,;P89LPC931FDH<SOT361-1 (TSSOP28)|<<http://www.nxp.com/packages/SOT361-1.html&l
文件页数: 8/55页
文件大小: 267K
代理商: P89LPC930FDH
Philips Semiconductors
P89LPC930/931
8-bit microcontrollers with two-clock 80C51 core
Product data
Rev. 05 — 15 December 2004
16 of 55
9397 750 14472
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
8.
Functional description
Remark: Please refer to the
P89LPC930/931 User’s Manual for a more detailed
functional description.
8.1 Enhanced CPU
The P89LPC930/931 uses an enhanced 80C51 CPU which runs at 6 times the speed
of standard 80C51 devices. A machine cycle consists of two CPU clock cycles, and
most instructions execute in one or two machine cycles.
8.2 Clocks
8.2.1
Clock denitions
The P89LPC930/931 device has several internal clocks as dened below:
OSCCLK — Input to the DIVM clock divider. OSCCLK is selected from one of four
clock sources (see Figure 4) and can also be optionally divided to a slower frequency
Note: fosc is dened as the OSCCLK frequency.
CCLK — CPU clock; output of the clock divider. There are two CCLK cycles per
machine cycle, and most instructions are executed in one to two machine cycles (two
or four CCLK cycles).
RCCLK — The internal 7.373 MHz RC oscillator output.
PCLK — Clock for the various peripheral devices and is CCLK/2
8.2.2
CPU clock (OSCCLK)
The P89LPC930/931 provides several user-selectable oscillator options in generating
the CPU clock. This allows optimization for a range of needs from high precision to
lowest possible cost. These options are congured when the FLASH is programmed
and include an on-chip Watchdog oscillator, an on-chip RC oscillator, an oscillator
using an external crystal, or an external clock source. The crystal oscillator can be
optimized for low, medium, or high frequency crystals covering a range from 20 kHz
to 12 MHz.
8.2.3
Low speed oscillator option
This option supports an external crystal in the range of 20 kHz to 100 kHz. Ceramic
resonators are also supported in this conguration.
8.2.4
Medium speed oscillator option
This option supports an external crystal in the range of 100 kHz to 4 MHz. Ceramic
resonators are also supported in this conguration.
8.2.5
High speed oscillator option
This option supports an external crystal in the range of 4 MHz to 18 MHz. Ceramic
resonators are also supported in this conguration. When using an oscillator
frequency above 12 MHz, the reset input function of P1.5 must be enabled. An
external circuit is required to hold the device in reset at power-up until VDD has
reached its specied level. When system power is removed VDD will fall below
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