参数资料
型号: P89LPC9351FA,112
厂商: NXP Semiconductors
文件页数: 61/94页
文件大小: 0K
描述: IC 80C51 MCU FLASH 8K 28-PLCC
产品培训模块: LPC9351/9321 Overview
标准包装: 2,368
系列: LPC900
核心处理器: 8051
芯体尺寸: 8-位
速度: 18MHz
连通性: I²C,SPI,UART/USART
外围设备: 欠压检测/复位,POR,PWM,温度传感器,WDT
输入/输出数: 26
程序存储器容量: 8KB(8K x 8)
程序存储器类型: 闪存
EEPROM 大小: 512 x 8
RAM 容量: 768 x 8
电压 - 电源 (Vcc/Vdd): 2.4 V ~ 3.6 V
数据转换器: A/D 8x8b; D/A 2x8b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 28-PLCC
包装: 管件
产品目录页面: 706 (CN2011-ZH PDF)
配用: 622-1014-ND - BOARD FOR LPC9XX TSSOP
622-1006-ND - SOCKET ADAPTER BOARD
568-4000-ND - DEMO BOARD SPI/I2C TO DUAL UART
568-3510-ND - DEMO BOARD SPI/I2C TO UART
568-1759-ND - EMULATOR DEBUGGER/PROGRMMR LPC9X
568-1758-ND - BOARD EVAL FOR LPC93X MCU FAMILY
其它名称: 568-4701-5
935287627112
P89LPC9351FA
P89LPC9331_9341_9351_9361
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5.1 — 20 August 2012
64 of 94
NXP Semiconductors
P89LPC9331/9341/9351/9361
8-bit microcontroller with accelerated two-clock 80C51 core
An early detection mechanism exists when the interrupt criteria has been selected to be
outside the boundary limits. In this case, after the four MSBs have been converted, these
four bits are compared with the four MSBs of the boundary high and low registers. If the
four MSBs of the conversion meet the interrupt criteria (i.e., outside the boundary limits)
an interrupt will be generated, if enabled. If the four MSBs do not meet the interrupt
criteria, the boundary limits will again be compared after all 8 bits have been converted.
The boundary status register (BNDSTA0) flags the channels which caused a boundary
interrupt.
8.9 DAC output to a port pin with high output impedance
Each ADC’s DAC block can be output to a port pin. In this mode, the ADxDAT3 register is
used to hold the value fed to the DAC. After a value has been written to the DAC (written
to ADxDAT3), the DAC output will appear on the channel 3 pin.
8.10 Clock divider
The ADC requires that its internal clock source be in the range of 320 kHz to 8 MHz to
maintain accuracy. A programmable clock divider that divides the clock from 1 to 8 is
provided for this purpose.
8.11 Power-down and Idle mode
In Idle mode the ADC, if enabled, will continue to function and can cause the device to exit
Idle mode when the conversion is completed if the A/D interrupt is enabled. In
Power-down mode or Total Power-down mode, the A/D, PGA and temperature sensor do
not function. If the PGAs, temperature sensor or the A/D are enabled, they will consume
power. Power can be reduced by disabling the PGA, temperature sensor and A/D.
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