参数资料
型号: P89LPC9401FBD,557
厂商: NXP Semiconductors
文件页数: 7/59页
文件大小: 0K
描述: IC 80C51 MCU FLASH 8K 64-LQFP
标准包装: 450
系列: LPC900
核心处理器: 8051
芯体尺寸: 8-位
速度: 18MHz
连通性: I²C,SPI,UART/USART
外围设备: 欠压检测/复位,LCD,LED,POR,PWM,WDT
输入/输出数: 23
程序存储器容量: 8KB(8K x 8)
程序存储器类型: 闪存
RAM 容量: 256 x 8
电压 - 电源 (Vcc/Vdd): 2.4 V ~ 3.6 V
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 64-LQFP
包装: 托盘
其它名称: 935278626557
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P89LPC9401_1
K
oninklijk
e
Philips
Electronics
N.V
.2005.
All
r
ights
reser
v
ed.
Preliminar
y
data
sheet
Re
v
.01
5
September
2005
15
of
59
Philips
Semiconductor
s
P89LPC9401
8-bit
tw
o-c
loc
k
80C51
micr
ocontr
oller
with
32
segment
×
4
LCD
driver
[1]
BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any are written while BRGEN = 1, the result is unpredictable.
[2]
All ports are in input only (high-impedance) state after power-up.
[3]
The RSTSRC register reects the cause of the P89LPC9401 reset. Upon a power-up reset, all reset source ags are cleared except POF and BOF; the power-on reset value is
xx11 0000.
[4]
The only reset source that affects these SFRs is power-on reset.
[5]
On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register.
[6]
After reset, the value is 1110 01x1, i.e., PRE2 to PRE0 are all logic 1, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after watchdog reset and is logic 0 after power-on reset.
Other resets will not affect WDTOF.
TAMOD
Timer 0 and 1 auxiliary
mode
8FH
-
T1M2
-
T0M2
00
xxx0 xxx0
Bit address
8F
8E
8D
8C
8B
8A
89
88
TCON*
Timer 0 and 1 control
88H
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
00
0000 0000
TH0
Timer 0 high
8CH
00
0000 0000
TH1
Timer 1 high
8DH
00
0000 0000
TL0
Timer 0 low
8AH
00
0000 0000
TL1
Timer 1 low
8BH
00
0000 0000
TL2
CCU timer low
CCH
00
0000 0000
TMOD
Timer 0 and 1 mode
89H
T1GATE
T1C/T
T1M1
T1M0
T0GATE
T0C/T
T0M1
T0M0
00
0000 0000
TRIM
Internal oscillator trim
register
96H
-
ENCLK
TRIM.5
TRIM.4
TRIM.3
TRIM.2
TRIM.1
TRIM.0
WDCON
Watchdog control register
A7H
PRE2
PRE1
PRE0
-
WDRUN
WDTOF
WDCLK
WDL
Watchdog load
C1H
FF
1111 1111
WFEED1
Watchdog feed 1
C2H
WFEED2
Watchdog feed 2
C3H
Table 4:
Special function registers …continued
* indicates SFRs that are bit addressable.
Name
Description
SFR
addr.
Bit functions and addresses
Reset value
MSB
LSB
Hex
Binary
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