参数资料
型号: P89LPC952FBD,157
厂商: NXP Semiconductors
文件页数: 4/69页
文件大小: 0K
描述: IC 80C51 MCU FLASH 8K 44-LQFD
产品培训模块: Migrating from 8/16-Bit MCUs to 32-Bit ARMs
标准包装: 800
系列: LPC900
核心处理器: 8051
芯体尺寸: 8-位
速度: 18MHz
连通性: I²C,SPI,UART/USART
外围设备: 欠压检测/复位,POR,PWM,WDT
输入/输出数: 40
程序存储器容量: 8KB(8K x 8)
程序存储器类型: 闪存
RAM 容量: 512 x 8
电压 - 电源 (Vcc/Vdd): 2.4 V ~ 3.6 V
数据转换器: A/D 8x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 44-LQFP
包装: 托盘
产品目录页面: 706 (CN2011-ZH PDF)
配用: 622-1016-ND - BOARD FOR P89LPC952FA 44-PLCC
622-1008-ND - BOARD FOR LPC9103 10-HVSON
OM10075-ND - EVAL BOARD FOR LPC952
568-4000-ND - DEMO BOARD SPI/I2C TO DUAL UART
568-3510-ND - DEMO BOARD SPI/I2C TO UART
622-1002-ND - USB IN-CIRCUIT PROG LPC9XX
568-1759-ND - EMULATOR DEBUGGER/PROGRMMR LPC9X
其它名称: 568-2014-5
935280152157
P89LPC952FBD
P89LPC952FDH-S
P89LPC952_954_4
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 24 July 2008
12 of 69
NXP Semiconductors
P89LPC952/954
8-bit microcontroller with 10-bit ADC
P2.5/SPICLK
27
31
25
I/O
P2.5 — Port 2 bit 5.
I/O
SPICLK — SPI clock. When congured as master, this pin is
output; when congured as slave, this pin is input.
P2.6
26
-
I/O
P2.6 — Port 2 bit 6.
P2.7
5
-
I/O
P2.7 — Port 2 bit 7.
P3.0 to P3.1
I/O
Port 3: Port 3 is a 2-bit I/O port with a user-congurable
output type. During reset Port 3 latches are congured in the
input only mode with the internal pull-up disabled. The
operation of Port 3 pins as inputs and outputs depends upon
the port conguration selected. Each port pin is congured
All pins have Schmitt triggered inputs.
Port 3 also provides various special functions as described
below:
P3.0/XTAL2/
CLKOUT
7
12
6
I/O
P3.0 — Port 3 bit 0.
O
XTAL2 — Output from the oscillator amplier (when a crystal
oscillator option is selected via the ash conguration.
O
CLKOUT — CPU clock divided by 2 when enabled via SFR
bit (ENCLK -TRIM.6). It can be used if the CPU clock is the
internal RC oscillator, watchdog oscillator or external clock
input, except when XTAL1/XTAL2 are used to generate clock
source for the RTC/system timer.
P3.1/XTAL1
6
11
5
I/O
P3.1 — Port 3 bit 1.
I
XTAL1 — Input to the oscillator circuit and internal clock
generator circuits (when selected via the ash conguration).
It can be a port pin if internal RC oscillator or watchdog
oscillator is used as the CPU clock source, and if
XTAL1/XTAL2 are not used to generate the clock for the
RTC/system timer.
P4.0 to P4.7
I/O
Port 4: Port 4 is an 8-bit I/O port with a user-congurable
output type. During reset Port 4 latches are congured in the
input only mode with the internal pull-up disabled. The
operation of Port 4 pins as inputs and outputs depends upon
the port conguration selected. Each port pin is congured
All pins have Schmitt triggered inputs.
Port 4 also provides various special functions as described
below:
P4.0
25
30
24
I/O
P4.0 — Port 4 bit 0.
P4.1/TRIG
24
29
23
I/O
P4.1 — Port 4 bit 1.
O
TRIG — Debugger trigger output.
P4.2/TXD1
23
28
22
I/O
P4.2 — Port 4 bit 2.
O
TXD1 — Transmitter output for serial port 1.
P4.3/RXD1
22
27
21
I/O
P4.3 — Port 4 bit 3.
I
RXD1 — Receiver input for serial port 1.
Table 3.
Pin description …continued
Symbol
Pin
Type Description
LQFP48
PLCC44
LQFP44
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