参数资料
型号: P89LPC972FDH,129
厂商: NXP Semiconductors
文件页数: 15/66页
文件大小: 0K
描述: MCU 80C51 8KB FLASH 20TSSOP
标准包装: 75
系列: LPC900
核心处理器: 8051
芯体尺寸: 8-位
速度: 18MHz
连通性: I²C,SPI,UART/USART
外围设备: 欠压检测/复位,POR,PWM,WDT
输入/输出数: 18
程序存储器容量: 8KB(8K x 8)
程序存储器类型: 闪存
RAM 容量: 256 x 8
电压 - 电源 (Vcc/Vdd): 2.4 V ~ 5.5 V
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 20-TSSOP(0.173",4.40mm 宽)
包装: 管件
其它名称: 568-8748-5
P89LPC972FDH,129-ND
P89LPC97X
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 3 — 8 June 2010
22 of 66
NXP Semiconductors
P89LPC970/971/972
8-bit microcontroller with accelerated two-clock 80C51 core
7.13 Memory organization
The various P89LPC970/971/972 memory spaces are as follows:
DATA
128 bytes of internal data memory space (00H:7FH) accessed via direct or indirect
addressing, using instructions other than MOVX and MOVC. All or part of the Stack
may be in this area.
IDATA
Indirect Data. 256 bytes of internal data memory space (00H:FFH) accessed via
indirect addressing using instructions other than MOVX and MOVC. All or part of the
Stack may be in this area. This area includes the DATA area and the 128 bytes
immediately above it.
SFR
Special Function Registers. Selected CPU registers and peripheral control and status
registers, accessible only via direct addressing.
XDATA
‘External’ Data or Auxiliary RAM. Duplicates the classic 80C51 64 kB memory space
addressed via the MOVX instruction using the DPTR, R0, or R1. All or part of this
space could be implemented on-chip.
CODE
64 kB of Code memory space, accessed as part of program execution and via the
MOVC instruction. The P89LPC970/971/972 has 4 kB/8 kB of on-chip Code memory.
7.14 Data RAM arrangement
The 768 bytes of on-chip RAM are organized as shown in Table 6.
7.15 Interrupts
The P89LPC970/971/972 uses a four priority level interrupt structure. This allows great
flexibility in controlling the handling of the many interrupt sources. The
P89LPC970/971/972 supports 15 interrupt sources: external interrupts 0 and 1, Timers 0
and 1, Timer 2/3/4, serial port TX, serial port RX, combined serial port RX/TX, brownout
detect, watchdog/RTC, I2C-bus, keyboard, comparators 1 and 2, SPI.
Each interrupt source can be individually enabled or disabled by setting or clearing a bit in
the interrupt enable registers IEN0 or IEN1. The IEN0 register also contains a global
disable bit, EA, which disables all interrupts.
Each interrupt source can be individually programmed to one of four priority levels by
setting or clearing bits in the interrupt priority registers IP0, IP0H, IP1 and IP1H. An
interrupt service routine in progress can be interrupted by a higher priority interrupt, but
Table 6.
On-chip data memory usages
Type
Data RAM
Size (bytes)
DATA
Memory that can be addressed directly and indirectly
128
IDATA
Memory that can be addressed indirectly
256
XDATA
Auxiliary (External Data) on-chip memory that is accessed
using the MOVX instructions
256
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