参数资料
型号: P89V660FA,512
厂商: NXP Semiconductors
文件页数: 7/90页
文件大小: 0K
描述: IC 80C51 MCU FLASH 16K 44-PLCC
产品培训模块: Migrating from 8/16-Bit MCUs to 32-Bit ARMs
标准包装: 1,300
系列: 89V
核心处理器: 8051
芯体尺寸: 8-位
速度: 40MHz
连通性: I²C,SPI,UART/USART
外围设备: POR,PWM,WDT
输入/输出数: 36
程序存储器容量: 16KB(16K x 8)
程序存储器类型: 闪存
RAM 容量: 512 x 8
电压 - 电源 (Vcc/Vdd): 4.5 V ~ 5.5 V
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 44-LCC(J 形引线)
包装: 管件
产品目录页面: 706 (CN2011-ZH PDF)
配用: 622-1001-ND - USB IN-CIRCUIT PROG 80C51ISP
其它名称: 568-2432-5
935280828512
P89V660FA
P89V660_662_664
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3.1 — 17 October 2011
15 of 90
NXP Semiconductors
P89V660/662/664
80C51 with 512 B/1 kB/2 kB RAM, dual I2C-bus, SPI
for the 89V662, above 6FFH for the 89V664) will access external off-chip memory and will
perform in the same way as the standard 8051, with P0 and P2 as data/address bus, and
P3[6] and P3[7] as write and read timing signals.
When EXTRAM = 0, MOVX @Ri and MOVX @DPTR will be similar to the standard 8051.
Using MOVX @Ri provides an 8-bit address with multiplexed data on Port 0. Other output
port pins can be used to output higher order address bits. This provides external paging
capabilities. Using MOVX @DPTR generates a 16-bit address. This allows external
addressing up the 64 kB. Port 2 provides the high-order eight address bits (DPH), and
Port 0 multiplexes the low order eight address bits (DPL) with data. Both MOVX @Ri and
MOVX @DPTR generates the necessary read and write signals (P3[6] - WR and P3[7] -
RD) for external memory use. Table 7 shows external data memory RD, WR operation
with EXTRAM bit.
The stack pointer (SP) can be located anywhere within the 256 B of internal RAM (lower
128 B and upper 128 B). The stack pointer may not be located in any part of the expanded
RAM.
Table 6.
AUXR - Auxiliary register (address 8EH) bit description
Bit
Symbol
Description
7 to 2
-
Reserved for future use. Should be set to ‘0’ by user programs.
1
EXTRAM
Internal/External RAM access using MOVX @Ri/@DPTR. When ‘1’,
accesses internal XRAM with address specified in MOVX instruction.
If address supplied with this instruction exceeds on-chip available
XRAM, off-chip RAM is accessed. When ‘0’, every MOVX instructions
targets external data memory by default.
0
AO
ALE off: disables/enables ALE. AO = 0 results in ALE emitted at a
constant rate of 12 the oscillator frequency. In case of AO = 1, ALE is
active only during a MOVX or MOVC.
Table 7.
External data memory RD, WR with EXTRAM bit
AUXR
MOVX @DPTR, A or MOVX A,
@DPTR
MOVX @Ri, A or MOVX A, @Ri
ADDR < 0100H
(89V660)
ADDR
0100H
(89V660)
ADDR = any
ADDR < 0300H
(89V662)
ADDR
0300H
(89V662)
ADDR < 0700H
(89V664)
ADDR
0700H
(89V664)
EXTRAM = 0
RD/WR asserted
EXTRAM = 1
RD/WR not
asserted
RD/WR asserted
RD/WR not asserted
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