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参数资料
型号： P95020ZLLGI8
厂商： INTEGRATED DEVICE TECHNOLOGY INC
元件分类： 电源管理
英文描述： 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, PBGA124
封装： LLGA-124
文件页数： 79/137页
文件大小： 3533K
代理商： P95020ZLLGI8
P95020 / Preliminary Datasheet
Revision 0.7.10
46
2010 Integrated Device Technology, Inc.
2.15.18 AUDIO - Digital Microphone (DMIC) Control Register
This register controls the Digital Microphone interface
DMIC_CTRL = IC Address = Page-1: 186(0xBA), C Address = 0xA1BA, Offset = 0xBA
Bit
Bit Name
Def.
Set.
User
Type
Value
Description / Comments
[1:0]
RATE
10b
RW
00b = 4.704 MHz
01b = 3.528 MHz
10b = 2.352 MHz
11b = 1.176 MHz
Selects the DMIC clock rate
[3:2]
PHADJ
00b
RW
0h = left data rising
edge/right data falling edge
1h = left data center of
high/right data center of low
2h = left data falling
edge/right data rising edge
3h = left data center of
low/right data center of high
DMIC sample phase adjust. Selects what phase of the DMIC clock
the Left / Mono data should be latched.
[5:4]
MODE
11b
RW
0h = Disabled - DMICCLK
held low.
A mute pattern (1010) is
sent to CIC
1h = Stereo on DMICDAT1
2h = Stereo on DMICDAT2
3h = Stereo using
DMICDAT1 as Left /
DMICDAT2 as Right
Selects DMIC input mode.
6
RESERVED
0b
RW
RESERVED
7
DMICCSEL
0b
RW
0 = DMICCSEL pin is low
1 = DMICCSEL pin is high
Logical value of DMICCSEL pin when port is in digital mode.
2.15.19 AUDIO - Analog Microphone Port Mode Control & Bias Register
The analog microphone port supports two independent microphone bias pins.
Each Microphone Bias pin can supply up to 3mA of current.
AMIC_CTRL = IC Address = Page-1: 187(0xBB), C Address = 0xA1BB, Offset = 0xBB
Bit
Bit Name
Def.
Set.
User
Type
Value
Description / Comments
[1:0]
MBIASL
00b
RW
00b = Hi-Z (off)
01b = 50% VDD_AUDIO33
10b = 90% VDD_AUDIO33
11b = GND
Left Microphone bias
[3:2]
MBIASR
00b
RW
00b = Hi-Z (off)
01b = 50% VDD_AUDIO33
10b = 90% VDD_AUDIO33
11b = GND
Right Microphone bias
[7:4]
RESERVED
0h
RW
RESERVED
2.15.20 AUDIO - AGC1 to AGC5 Automatic Gain Control Registers
AGCSET1 = IC Address = Page-1: 188(0xBC), C Address = 0xA1BC
Bit
Bit Name
Def.
Set.
User
Type
Value
Description / Comments
[3:0]
TARGET
2h
RW
Gain control programmable in 1.5 dB steps. For example 0h = 0 dB, ,
1h = -1.5 dB and Fh = -22.5 dB.
[7:4]
DELAY
2h
RW
Delay Time =
2^(x+6)*base_time sec
Delay base time is
configured by
{basetime_ctrl_sign, mag}
Delay Time: BASETIME_CTRL_SIGN and BASETIME_CTRL_MAG
(0xBF bit[7] and bit[6:5]) defines AGC function operation basetime
unit.
AGCSET2 = IC Address = Page-1: 189(0xBD), C Address = 0xA1BD
Bit
Bit Name
Def.
Set.
User
Type
Value
Description / Comments
[3:0]
ATTACK
0h
RW
2^(n+9)*base_time, n>10,
use n=10
Attack time is the time that it takes the AGC to ramp down across its
gain range.
[7:4]
DECAY
0h
RW
2^(n+11)*base_time
Attack time is the time that it takes the AGC to ramp up across its
gain range
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