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参数资料
型号： P95020ZLLGI8
厂商： INTEGRATED DEVICE TECHNOLOGY INC
元件分类： 电源管理
英文描述： 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, PBGA124
封装： LLGA-124
文件页数： 85/137页
文件大小： 3533K
代理商： P95020ZLLGI8
P95020 / Preliminary Datasheet
Revision 0.7.10
51
2010 Integrated Device Technology, Inc.
2.15.30 AUDIO - Audio Subsection Power Control 1 Register
IC Address = Page-1: 209(0xD1), C Address = 0xA1D1, Offset = 0xD1
The Audio Subsection provides gross and fine power control. This register controls large blocks of the Audio Subsection.
Bit
Bit Name
Def.
Set.
User
Type
Value
Description / Comments
0
LINE_IN_D2S_PWD
0b
RW
0 = Not powered down
1 = Powered down
Line Input D2S power down
1
DIG _PWD
0b
RW
0 = Not powered down
1 = Powered down
DIGITAL path power down (IS)
2
VREF_PWD
0b
RW
0 = Not powered down
1 = Powered down
Reference power down
3
ADC_PWD
0b
RW
0 = Not powered down
1 = Powered down
ADC power down
4
DAC_PWD
0b
RW
0 = Not powered down
1 = Powered down
DAC power down
5
STANDBY
0b
RW
0 = Normal operation
1 = Standby mode
Low power mode
[7:6]
RESERVED
RW
RESERVED
2.15.31 AUDIO - Audio Subsection Power Control 2 Register
IC Address = Page-1: 210(0xD2), C Address = 0xA1D2, Offset = 0xD2
The Audio Subsection provides gross and fine power control. This register controls individual DAC and ADC channels of
the Audio Subsection.
Bit
Bit Name
Def.
Set.
User
Type
Value
Description / Comments
0
DAC0L_PWD
0b
RW
0 = Not powered down
1 = Powered down
Power down Left half of DAC0
1
DAC0R_PWD
0b
RW
0 = Not powered down
1 = Powered down
Power down Right half of DAC0
2
DAC1L_PWD
0b
RW
0 = Not powered down
1 = Powered down
Power down Left half of DAC1
3
DAC1R_PWD
0b
RW
0 = Not powered down
1 = Powered down
Power down Right half of DAC1
4
ADC0L_PWD
0b
RW
0 = Not powered down
1 = Powered down
Power down Left half of ADC0
5
ADC0R_PWD
0b
RW
0 = Not powered down
1 = Powered down
Power down Right half of ADC0
6
ADC1L_PWD
0b
RW
0 = Not powered down
1 = Powered down
Power down Left half of ADC1
7
ADC1R_PWD
0b
RW
0 = Not powered down
1 = Powered down
Power down Right half of ADC1
2.15.32 AUDIO - Audio Subsection Power Control 3 Register
IC Address = Page-1: 211(0xD3), C Address = 0xA1D3, Offset = 0xD3
The Audio Subsection provides gross and fine power control. This register controls individual DAC and ADC channels of
the Audio Subsection.
Bit
Bit Name
Def.
Set.
User
Type
Value
Description / Comments
0
RESERVED
0h
RW
RESERVED
1
HP_VIRTBUF_PWD
0b
RW
0 = Not powered down
1 = Powered down
Power down Headphone Virtual Ground Buffer
2
HP_RIGHT_PWD
0b
RW
0 = Not powered down
1 = Powered down
Power down Right channel of Headphone out
3
HP_LEFT_PWD
0b
RW
0 = Not powered down
1 = Powered down
Power down Left channel of Headphone out
4
LINEOUT_RIGHT_PWD
0b
RW
0 = Not powered down
1 = Powered down
Power down Right channel of Line out
5
LINEOUT_LEFT_PWD
0b
RW
0 = Not powered down
1 = Powered down
Power down Left channel of Line out
6
ADC2_RIGHT_PWD
0b
RW
0 = Not powered down
1 = Powered down
Power down Right half of ADC2
7
ADC2_LEFT_PWD
0b
RW
0 = Not powered down
1 = Powered down
Power down Left half of ADC2
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