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参数资料
| 型号： | PA28F200BL-T150 |
| 厂商： | INTEL CORP |
| 元件分类： | PROM |
| 英文描述： | 2-MBIT (128K x 16, 256K x 8)LOW-POWER BOOT BLOCK FLASH MEMORY FAMILY |
| 中文描述： | 128K X 16 FLASH 12V PROM, 150 ns, PDSO44 |
| 封装： | 1.110 X 0.525 INCH, PLASTIC, SOP-44 |
| 文件页数： | 17/48页 |
| 文件大小： | 562K |
| 代理商： | PA28F200BL-T150 |
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28F200BX-T/B, 28F002BX-T/B
4.2 28F002BX Bus Operations
Table 3. Bus Operations
Mode
Notes
RP
Y
CE
Y
OE
Y
WE
Y
A
9
A
0
V
PP
DQ
0–7
Read
1, 2
V
IH
V
IL
V
IL
V
IH
X
X
X
D
OUT
Output Disable
V
IH
V
IL
V
IH
V
IH
X
X
X
High Z
Standby
V
IH
V
IH
X
X
X
X
X
High Z
Deep Power-Down
9
V
IL
X
X
X
X
X
X
High Z
Intelligent Identifier (Mfr)
3, 4
V
IH
V
IL
V
IL
V
IH
V
ID
V
IL
X
89H
Intelligent Identifier (Device)
3, 4, 5
V
IH
V
IL
V
IL
V
IH
V
ID
V
IH
X
7CH
7DH
Write
6, 7, 8
V
IH
V
IL
V
IH
V
IL
X
X
X
D
IN
NOTES:
1. Refer to DC Characteristics.
2. X can be V
IL
or V
IH
for control pins and addresses, V
PPL
or V
PPH
for V
PP
.
3. See DC characteristics for V
PPL
, V
PPH
, V
HH
, V
ID
voltages.
4. Manufacturer and Device codes may also be accessed via a CUI write sequence. A
1
–A
16
e
X.
5. Device ID
e
7CH for 28F002BX-T and 7DH for 28F002BX-B.
6. Refer to Table 4 for valid D
IN
during a write operation.
7. Command writes for Block Erase or byte program are only executed when V
PP
e
V
PPH
.
8. Program or erase the Boot block by holding RP
Y
at V
HH
.
9. RP
Y
must be at GND
g
0.2V to meet the 1.2
m
A maximum deep power-down current.
4.3 Read Operations
The 2-Mbit boot block flash family has three user
read modes; Array, Intelligent Identifier, and Status
Register. Status Register read mode will be dis-
cussed in detail in the ‘‘Write Operations’’ section.
During power-up conditions (V
CC
supply ramping), it
takes a maximum of 600 ns from when V
CC
is at
4.5V minimum to valid data on the outputs.
4.3.1 READ ARRAY
If the memory is not in the Read Array mode, it is
necessary to write the appropriate read mode com-
mand to the CUI. The 2-Mbit boot block flash family
has three control functions, all of which must be
logically active, to obtain data at the outputs.
Chip-Enable CE
Y
is the device selection control.
Power-Down RP
Y
is the device power control. Out-
put-Enable OE
Y
is the DATA INPUT/OUTPUT
(DQ
[
0:15
]
or DQ
[
0:7
]
) direction control and when
active is used to drive data from the selected memo-
ry on to the I/O bus.
4.3.1.1 Output Control
With OE
Y
at logic-high level (V
IH
), the output from
the device is disabled and data input/output pins
(DQ
[
0:15
]
or DQ
[
0:7
]
) are tri-stated. Data input is
then controlled by WE
Y
.
4.3.1.2 Input Control
With WE
Y
at logic-high level (V
IH
), input to the de-
vice is disabled. Data Input/Output pins (DQ-
[
0:15
]
or DQ
[
0:7
]
) are controlled by OE
Y
.
4.3.2 INTELLIGENT IDENTlFlERS
28F200BX Products
The manufacturer and device codes are read via the
CUI or by taking the A
9
pin to 12V. Writing 90H to
the CUI places the device into Intelligent Identifier
read mode. A read of location 00000H outputs the
manufacturer’s identification code, 0089H, and loca-
tion 00001H outputs the device code; 2274H for
28F200BX-T,
2275H
for
BYTE
Y
is at a logic low only the lower byte of the
above signatures is read and DQ
15
/A
b
1
is a ‘‘don’t
care’’ during Intelligent Identifier mode. A read array
command must be written to the CUI to return to the
read array mode.
28F200BX-B.
When
17
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