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参数资料
| 型号： | PA28F200BL-T150 |
| 厂商： | INTEL CORP |
| 元件分类： | PROM |
| 英文描述： | 2-MBIT (128K x 16, 256K x 8)LOW-POWER BOOT BLOCK FLASH MEMORY FAMILY |
| 中文描述： | 128K X 16 FLASH 12V PROM, 150 ns, PDSO44 |
| 封装： | 1.110 X 0.525 INCH, PLASTIC, SOP-44 |
| 文件页数： | 8/48页 |
| 文件大小： | 562K |
| 代理商： | PA28F200BL-T150 |
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28F200BX-T/B, 28F002BX-T/B
1.5 Pin Descriptions for the x8/x16 28F200BX
Symbol
Type
Name and Function
A
0
–A
16
I
ADDRESS INPUTS
for memory addresses. Addresses are internally latched
during a write cycle.
A
9
I
ADDRESS INPUT:
When A
is at 12V the signature mode is accessed. During this
mode A
0
decodes between the manufacturer and device ID’s. When BYTE
Y
is at
a logic low only the lower byte of the signatures are read. DQ
15
/A
b
1
is a don’t
care in the signature mode when BYTE
Y
is low.
DQ
0
–DQ
7
I/O
DATA INPUTS/OUTPUTS:
Inputs array data on the second CE
Y
and WE
Y
cycle
during a program command. Inputs commands to the Command User Interface
when CE
Y
and WE
Y
are active. Data is internally latched during the write and
program cycles. Outputs array, Intelligent Identifier and Status Register data. The
data pins float to tri-state when the chip is deselected or the outputs are disabled.
DQ
8
–DQ
15
I/O
DATA INPUTS/OUTPUTS:
Inputs array data on the second CE
Y
and WE
Y
cycle
during a program command. Data is internally latched during the write and program
cycles. Outputs array data. The data pins float to tri-state when the chip is
deselected or the outputs are disabled as in the byte-wide mode (BYTE
Y
e
‘‘0’’).
In the byte-wide mode DQ
15
/A
b
1
becomes the lowest order address for data
output on DQ
0
–DQ
7
.
CHIP ENABLE:
Activates the device’s control logic, input buffers, decoders and
sense amplifiers. CE
Y
is active low; CE
Y
high deselects the memory device and
reduces power consumption to standby levels. If CE
Y
and RP
Y
are high, but not
at a CMOS high level, the standby current will increase due to current flow through
the CE
Y
and RP
Y
input stages.
CE
Y
I
RP
Y
I
RESET/DEEP POWER-DOWN:
Provides three-state control. Puts the device in
deep power-down mode. Locks the boot block from program/erase.
When RP
Y
is at logic high level and equals 6.5V maximum the boot block is
locked and cannot be programmed or erased.
When RP
Y
e
11.4V minimum the boot block is unlocked and can be programmed
or erased.
When RP
Y
is at a logic low level the boot block is locked, the deep power-down
mode is enabled and the WSM is reset preventing any blocks from being
programmed or erased, therefore providing data protection during power
transitions. When RP
Y
transitions from logic low to logic high the flash memory
enters the read array mode.
OE
Y
I
OUTPUT ENABLE:
Gates the device’s outputs through the data buffers during a
read cycle. OE
Y
is active low.
WE
Y
I
WRITE ENABLE:
Controls writes to the Command Register and array blocks.
WE
Y
is active low. Addresses and data are latched on the rising edge of the WE
Y
pulse.
BYTE
Y
I
BYTE
Y
ENABLE:
Controls whether the device operates in the byte-wide mode
(x8) or the word-wide mode (x16). BYTE
Y
pin must be controlled at CMOS levels
to meet 100
m
A CMOS current in the standby mode. BYTE
Y
e
‘‘0’’ enables the
byte-wide mode, where data is read and programmed on DQ
0
–DQ
7
and
DQ
15
/A
b
1
becomes the lowest order address that decodes between the upper
and lower byte. DQ
–DQ
are tri-stated during the byte-wide mode.
BYTE
Y
e
‘‘1’’ enables the word-wide mode where data is read and programmed
on DQ
0
–DQ
15
.
PROGRAM/ERASE POWER SUPPLY:
For erasing memory array blocks or
programming data in each block.
Note:
V
PP
k
V
PPLMAX
memory contents cannot be altered.
DEVICE POWER SUPPLY (5V
g
10%, 5V
g
5%)
GROUND:
For all internal circuitry.
V
PP
V
CC
GND
NC
NO CONNECT:
Pin may be driven or left floating.
DU
DON’T USE PIN:
Pin should not be connected to anything.
8
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