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参数资料
| 型号： | PA28F400B5B80 |
| 厂商： | INTEL CORP |
| 元件分类： | PROM |
| 英文描述： | SMART 5 BOOT BLOCK FLASH MEMORY FAMILY 2, 4, 8 MBIT |
| 中文描述： | 512K X 8 FLASH 5V PROM, 80 ns, PDSO44 |
| 封装： | 0.525 X 1.110 INCH, PLASTIC, SOP-44 |
| 文件页数： | 7/38页 |
| 文件大小： | 501K |
| 代理商： | PA28F400B5B80 |
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E
SMART 5 BOOT BLOCK MEMORY FAMILY
7
ADVANCE INFORMATION
Table 2. Pin Descriptions
Symbol
Type
Name and Function
A
0
–A
18
INPUT
ADDRESS INPUTS
for memory addresses. Addresses are internally latched
during a write cycle.
28F200: A[0
–16], 28F400: A[0–17], 28F800: A[0–18], 28F004: A[0–18]
ADDRESS INPUT:
When A
9
is at V
HH
the signature mode is accessed. During
this mode, A
0
decodes between the manufacturer and device IDs. When BYTE#
is at a logic low, only the lower byte of the signatures are read. DQ
15
/A
–1
is a
don’t care in the signature mode when BYTE# is low.
A
9
INPUT
DQ
0
–DQ
7
INPUT/
OUTPUT
DATA INPUTS/OUTPUTS:
Inputs array data on the second CE# and WE# cycle
during a Program command. Inputs commands to the Command User Interface
when CE# and WE# are active. Data is internally latched during the write cycle.
Outputs array, intelligent identifier and status register data. The data pins float to
tri-state when the chip is de-selected or the outputs are disabled.
DQ
8
–DQ
15
INPUT/
OUTPUT
DATA INPUTS/OUTPUTS:
Inputs array data on the second CE# and WE# cycle
during a Program command. Data is internally latched during the write cycle.
Outputs array data. The data pins float to tri-state when the chip is de-selected or
the outputs are disabled as in the byte-wide mode (BYTE# = “0”). In the byte-wide
mode DQ
15
/A
–1
becomes the lowest order address for data output on DQ
0
–DQ
7
.
Not applicable to 28F004B5.
CE#
INPUT
CHIP ENABLE:
Activates the device’s control logic, input buffers, decoders and
sense amplifiers. CE# is active low. CE# high de-selects the memory device and
reduces power consumption to standby levels. If CE# and RP# are high, but not
at a CMOS high level, the standby current will increase due to current flow
through the CE# and RP# input stages.
OE#
INPUT
OUTPUT ENABLE:
Enables the device’s outputs through the data buffers during
a read cycle. OE# is active low.
WE#
INPUT
WRITE ENABLE:
Controls writes to the command register and array blocks. WE#
is active low. Addresses and data are latched on the rising edge of the WE#
pulse.
RP#
INPUT
RESET/DEEP POWER-DOWN:
Uses three voltage levels (V
IL
, V
IH
, and V
HH
) to
control two different functions: reset/deep power-down mode and boot block
unlocking. It is backwards-compatible with the BX/BL/BV products.
When RP# is at logic low, the device is in reset/deep power-down mode
,
which puts the outputs at High-Z, resets the Write State Machine, and draws
minimum current.
When RP# is at logic high, the device is in standard operation
. When RP#
transitions from logic-low to logic-high, the device defaults to the read array mode.
When RP# is at V
HH
, the boot block is unlocked
and can be programmed or
erased. This overrides any control from the WP# input.
相关PDF资料 |
PDF描述 |
|---|---|
| PA28F800B5B90 | SMART 5 BOOT BLOCK FLASH MEMORY FAMILY 2, 4, 8 MBIT |
| PA28F200B5T60 | SMART 5 BOOT BLOCK FLASH MEMORY FAMILY 2, 4, 8 MBIT |
| PA28F400B5T60 | SMART 5 BOOT BLOCK FLASH MEMORY FAMILY 2, 4, 8 MBIT |
| PA28F800B5T70 | SMART 5 BOOT BLOCK FLASH MEMORY FAMILY 2, 4, 8 MBIT |
| PA28F200B5T80 | SMART 5 BOOT BLOCK FLASH MEMORY FAMILY 2, 4, 8 MBIT |
相关代理商/技术参数 |
参数描述 |
|---|---|
| PA28F400B5T60 | 制造商:Intel 功能描述: |
| PA28F400B5T80 | 制造商:Intel 功能描述:Flash Mem Parallel 5V 4M-Bit 512K x 8/256K x 16 80ns 44-Pin SOP |
| PA28F400BL-B150 | 制造商:INTEL 制造商全称:Intel Corporation 功能描述:4-MBlT (256K x 16, 512K x 8) LOW-POWER BOOT BLOCK FLASH MEMORY FAMILY |
| PA28F400BL-T150 | 制造商:INTEL 制造商全称:Intel Corporation 功能描述:4-MBlT (256K x 16, 512K x 8) LOW-POWER BOOT BLOCK FLASH MEMORY FAMILY |
| PA28F400BVB120 | 制造商:INTEL 制造商全称:Intel Corporation 功能描述:4-MBIT (256K X 16, 512K X 8)SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY |
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