- 您现在的位置：买卖IC网 > PDF目录367750 > PA28F400BX-T80 (INTEL CORP) 4-MBIT (256K X 16, 512K X 8) BOOT BLOCK FLASH MEMORY FAMILY PDF资料下载
参数资料
| 型号： | PA28F400BX-T80 |
| 厂商： | INTEL CORP |
| 元件分类： | PROM |
| 英文描述： | 4-MBIT (256K X 16, 512K X 8) BOOT BLOCK FLASH MEMORY FAMILY |
| 中文描述： | 256K X 16 FLASH 12V PROM, 80 ns, PDSO40 |
| 封装： | 1.110 X 0.525 INCH, PLASTIC, SOP-40 |
| 文件页数： | 9/50页 |
| 文件大小： | 559K |
| 代理商： | PA28F400BX-T80 |
第1页第2页第3页第4页第5页第6页第7页第8页当前第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页
28F400BX-T/B, 28F004BX-T/B
1.5 28F400BX Pin Descriptions
Symbol
Type
Name and Function
A
0
–A
17
I
ADDRESS INPUTS
for memory addresses. Addresses are internally latched during a write
cycle.
A
9
I
ADDRESS INPUT:
When A
9
is at 12V the signature mode is accessed. During this mode A
0
decodes between the manufacturer and device ID’s. When BYTE
Y
is at a logic low only the
lower byte of the signatures are read. DQ
15
/A
b
1
is a don’t care in the signature mode when
BYTE
Y
is low.
DQ
0
–DQ
7
I/O
DATA INPUTS/OUTPUTS:
Inputs array data on the second CE
Y
and WE
Y
cycle during a
program command. Inputs commands to the command user interface when CE
Y
and WE
Y
are active. Data is internally latched during the write and program cycles. Outputs array,
Intelligent Identifier and Status Register data. The data pins float to tri-state when the chip is
deselected or the outputs are disabled.
DQ
8
–DQ
15
I/O
DATA INPUTS/OUTPUTS:
Inputs array data on the second CE
Y
and WE
Y
cycle during a
program command. Data is internally latched during the write and program cycles. Outputs
array data. The data pins float to tri-state when the chip is deselected or the outputs are
disabled as in the byte-wide mode (BYTE
Y
e
‘‘0’’). In the byte-wide mode DQ
15
/A
b
1
becomes the lowest order address for data output on DQ
0
-DQ
7
.
CE
Y
I
CHIP ENABLE:
Activates the device’s control logic, input buffers, decoders and sense
amplifiers. CE
Y
is active low; CE
Y
high deselects the memory device and reduces power
consumption to standby levels. If CE
Y
and RP
Y
are high, but not at a CMOS high level, the
standby current will increase due to current flow through the CE
Y
and RP
Y
input stages.
RP
Y
I
RESET/DEEP POWER-DOWN:
Provides three-state control. Puts the device in deep power-
down mode. Locks the boot block from program/erase.
When RP
Y
is at logic high level and equals 6.5V maximum the boot block is locked and
cannot be programmed or erased.
When RP
Y
e
11.4V minimum the boot block is unlocked and can be programmed or
erased.
When RP
Y
is at a logic low level the boot block is locked, the deep power-down mode is
enabled and the WSM is reset preventing any blocks from being programmed or erased,
therefore providing data protection during power transitions.
When RP
Y
transitions from logic low to logic high the flash memory enters the read-array
mode.
OE
Y
I
OUTPUT ENABLE:
Gates the device’s outputs through the data buffers during a read cycle.
OE
Y
is active low.
WE
Y
I
WRITE ENABLE:
Controls writes to the Command Register and array blocks. WE
Y
is active
low. Addresses and data are latched on the rising edge of the WE
Y
pulse.
BYTE
Y
I
BYTE
Y
ENABLE:
Controls whether the device operates in the byte-wide mode (x8) or the
word-wide mode (x16). BYTE
Y
pin must be controlled at CMOS levels to meet 100A CMOS
current in the standby mode. BYTE
Y
e
‘‘0’’ enables the byte-wide mode, where data is read
and programmed on DQ
0
–DQ
7
and DQ
15
/A
b
1
becomes the lowest order address that
decodes between the upper and lower byte. DQ
8
–DQ
14
are tri-stated during the byte-wide
mode. BYTE
Y
e
‘‘1’’ enables the word-wide mode where data is read and programmed on
DQ
0
–DQ
15
.
V
PP
PROGRAM/ERASE POWER SUPPLY:
For erasing memory array blocks or programming
data in each block.
Note:
V
PP
k
V
PPLMAX
memory contents cannot be altered.
V
CC
DEVICE POWER SUPPLY (5V
g
10%, 5V
g
5%)
GND
GROUND:
For all internal circuitry.
NC
NO CONNECT:
Pin may be driven or left floating.
DU
DON’T USE PIN:
Pin should not be connected to anything.
9
相关PDF资料 |
PDF描述 |
|---|---|
| PA28F400CV-B80 | 2-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY |
| PA28F400CV-T60 | 2-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY |
| PA28F400CV-T80 | 2-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY |
| PA28F400BL-T150 | ECONOLINE: RM & RL - Single Output Rail- Industry Standard Pinout- 1kVDC & 2kVDC Isolation- High Efficiency for Low Power Applications- UL94V-0 Package Material- Toroidal Magnetics- Fully Encapsulated- Efficiency to 80% |
| PA28F400BV-T60 | POWERLINE: RP40-S_D_TE - 2:1 Wide Input Voltage Range- 40 Watts Output Power- 1.6kVDC Isolation- Fixed Operating Frequency- Six-Sided Continuous Shield- Design Meet Safety Standard- Standard 76.2 x66.0x10.2mm Package- Efficiency to 90% |
相关代理商/技术参数 |
参数描述 |
|---|---|
| PA28F400CV-B60 | 制造商:INTEL 制造商全称:Intel Corporation 功能描述:2-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY |
| PA28F400CV-B80 | 制造商:INTEL 制造商全称:Intel Corporation 功能描述:2-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY |
| PA28F400CV-T60 | 制造商:INTEL 制造商全称:Intel Corporation 功能描述:2-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY |
| PA28F400CV-T80 | 制造商:INTEL 制造商全称:Intel Corporation 功能描述:2-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY |
| PA28F800B5B70 | 制造商:INTEL 制造商全称:Intel Corporation 功能描述:SMART 5 BOOT BLOCK FLASH MEMORY FAMILY 2, 4, 8 MBIT |
发布紧急采购，3分钟左右您将得到回复。