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参数资料
| 型号： | PBL386402QNT |
| 厂商： | ERICSSON |
| 英文描述： | Subscriber Line Interface Circuit |
| 中文描述： | 用户线接口电路 |
| 文件页数： | 13/16页 |
| 文件大小： | 138K |
| 代理商： | PBL386402QNT |
PBL 386 40/2
13
Figure 12. Single-channel subscriber line interface with PBL 386 40/2 and combination CODEC/filter.
RESISTORS: (Values according to IEC E96 series)
R
SG
= 0
R
LD
= 49.9 k
R
OV
= User programmable
R
LC
= 32.4 k
R
REF
= 49.9 k
R
R
= 64.9 k
R
T
= 105 k
R
TX
= 24.9 k
R
B
= 22.1 k
R
RX
= 52.3 k
R
FB
Depending on CODEC / filter
R
1
= 604 k
R
2
= 604 k
R
3
= 249 k
R
4
= 280 k
R
RT
= 330
R
P1
, R
P2
= 10
R
F1
, R
F2
= Line resistor, 40
1% match
1% 1/10 W
1% 1/10 W
1% 1/10 W
1% 1/10 W
1% 1/10 W
1% 1/10 W
1% 1/10 W
1% 1/10 W
1% 1/10 W
1% 1/10 W
1% 1/10 W
1% 1/10 W
1% 1/10 W
5% 2 W
1% 1/10 W (Note 1)
CAPACITORS: (Values according to IEC E96
series)
C
VB
= 100 nF
C
VB2
= 150 nF
C
VCC
= 100 nF
C
TC
= 2.2 nF
C
RC
= 2.2 nF
C
HP
= 47 nF
C
LP
= 150 nF
C
TX
= 100 nF
C
GG
= 220 nF
C
1
= 330 nF
C
2
= 330 nF
100 V 10%
100 V 10%
10 V 10%
100 V 10%
100 V 10%
100 V 10%
100 V 10%
10 V 10%
100 V 10%
63 V 10%
63 V 10%
DIODES:
D
VB
D
VB2
D
BB
D
HP
= 1N4448
= 1N4448
= 1N4448
= 1N4448 (Note 2)
OVP:
Secondary protection (e.g. Power
Innovations TISPPBL2). The ground
terminals of the secondary protection should
be connected to the common ground on the
Printed Board Assembly with a track as
short and wide as possible, preferable a
groundplane.
R
LC
R
RX
R
REF
R
LD
C
VCC
C
TX
PBL 386 40/2
R
TX
0
0
CODEC/
Filter
R
FB
SYSTEM CONTROL
INTERFACE
R
R
R
T
R
B
-
+
VCC
VCC
BGND
TIPX
VBAT
VBAT2
PLC
POV
PLD
VCC
PSG
NC
LP
DT
NC
DET
C1
C2
RRLY
HP
NC
RINGX
AGND
RSN
NC
REF
PTG
VTX
DR
C3
PBL 386 40/2
R
OV
R
SG
C
LP
C
1
R
4
C
2
R
3
C
HP
VB2
SLIC No. 2 etc.
C
RC
R
P2
R
P1
R
F2
R
F1
TIP
RING
OVP
C
GG
C
TC
VB
+12 V /+5V
K
R
C
VB
D
VB2
C
VB2
D
BB
VB
D
VB
R
RT
E
RG
R
2
R
1
D
HP
and AGND, the overhead voltage can be
set to higher values, typical values can
be seen in figure 11. The R
and
corresponding V
(signal headroom)
are typical values for THD <1% and the
signal frequency 1000Hz.
Observe that the 4-wire output terminal
V
can not handle more than 3,2 V
Peak.
So if the gain 2-wire to 4-wire is 0dB,
3,2 V
is maximum also for the 2-wire
side. Signal levels between 3,2 and
6,4 V
on the 2-wire side can be
handled with the PTG shorted so that the
gain G
become -6,02dB. Please note
that the 2-wire impedance, R
and the
4-wire to 4-wire gain has to be recalcu-
lated if the PTG is shorted.
Please note that the maximum signal
current at the 2-wire side can not be
greater than 9 mA.
How to use POV:
1. Decide what overhead voltage(V
)
is needed. The POV function is only
needed if the overhead voltage
exceeds 3,2 V
2. In figure 11 the corresponding R
OV
for
the decided V
can be found.
3. If the overhead voltage exceeds
3,2 V
, the G
gain has to be
changed to -6,02dB by connecting
the PTG pin to AGND. Please note
that the two-wire impedance, R
and
the 4-wire to 4-wire gain has to be
recalculated.
Analog Temperature Guard
The widely varying environmental
conditions in which SLICs operate may
lead to the chip temperature limitations
being exceeded. The PBL 386 40/2 SLIC
reduce the dc line current when approxi-
mately 145
°
C and increases it again
automatically when the temperature
drops. Accordingly transmission is not
lost under high ambient temperature
conditions.
The detector output, DET, is forced to
a logic low level when the temperature
guard is active.
NOTES:
1. R
P1
and R
P2
may be omitted if D
VB
is in place.
2. It is required to connect D
HP
between terminal
HP and ground if C
HP
> 47nF
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