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参数资料
| 型号： | PC13892VLR2 |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 电源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PBGA186 |
| 封装： | 12 X 12 MM, 0.80 MM PITCH, ROHS COMPLIANT, PLASTIC, BGA-186 |
| 文件页数： | 32/75页 |
| 文件大小： | 3848K |
| 代理商： | PC13892VLR2 |
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Analog Integrated Circuit Device Data
38
Freescale Semiconductor
13892
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages.
TIMING DIAGRAMS
timing requirements. The SPI input and output levels are set
independently via the SPIVCC pin by connecting it to the
desired supply. This would typically be tied to SW4
programmed for 1.80 V. The strength of the MISO driver is
programmable through the SPIDRV[1:0] bits.
Figure 5. Timing Requirements
Table 7. Timing Parameter Description
PARAMETER
DESCRIPTION
T MIN (NS)
tSELSU
Time CS has to be high before the first rising edge of CLK
15
tSELHID
Time CS has to remain high after the last falling edge of CLK
15
tSELLOW
Time CS has to remain low between two transfers
15
tCLKPER
Clock period of CLK
38
tCLKHIGH
Part of the clock period where CLK has to remain high
15
tCLKLOW
Part of the clock period where CLK has to remain low
15
tWRTSU
Time MOSI has to be stable before the next rising edge of CLK
4.0
tWRTHLD
Time MOSI has to remain stable after the rising edge of CLK
4.0
tRDSU
Time MISO will be stable before the next rising edge of CLK
4.0
tRDHLD
Time MISO will remain stable after the falling edge of CLK
4.0
tRDEN
Time MISO needs to become active after the rising edge of CS
4.0
tRDDIS
Time MISO needs to become inactive after the falling edge of CS
4.0
Notes
41.
This table reflects a maximum SPI clock frequency of 26 MHz. Slew rate for SPI MISO output driver is programmable from 0.16 to
0.66 V/ns
CS
CLK
MOSI
MISO
TSELSU
TWRTSU
TRDEN
TWRTHLD
TRDSU
TCLKPER
TCLKHIGH
TCLKLOW
TRDHLD
TSELHLD
TSELLOW
TRDDIS
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